f8f1a91cf7
Update driver code and board files to use new GPIO configuration flags such as GPIO_ACTIVE_LOW. Also add implementation of new port_* driver API as well as gpio_pin_interrupt_configure function. The interrupt triggering on both edges is a remnant from the old Quark SE which has a customized DesignWare GPIO block. So remove the support for both edges as the board is no longer supported. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
47 lines
1.2 KiB
C
47 lines
1.2 KiB
C
/*gpio_dw_registers.h - Private gpio's registers header*/
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/*
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* Copyright (c) 2015 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_GPIO_GPIO_DW_REGISTERS_H_
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#define ZEPHYR_DRIVERS_GPIO_GPIO_DW_REGISTERS_H_
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/** This definition of GPIO related registers supports four ports: A, B, C, D
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* yet only PORTA supports interrupts and debounce.
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*/
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#define SWPORTA_DR 0x00
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#define SWPORTA_DDR 0x04
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#define SWPORTA_CTL 0x08
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#define SWPORTB_DR 0x0c
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#define SWPORTB_DDR 0x10
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#define SWPORTB_CTL 0x14
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#define SWPORTC_DR 0x18
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#define SWPORTC_DDR 0x1c
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#define SWPORTC_CTL 0x20
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#define SWPORTD_DR 0x24
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#define SWPORTD_DDR 0x28
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#define SWPORTD_CTL 0x2c
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#define INTEN 0x30
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#define INTMASK 0x34
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#define INTTYPE_LEVEL 0x38
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#define INT_POLARITY 0x3c
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#define INTSTATUS 0x40
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#define RAW_INTSTATUS 0x44
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#define PORTA_DEBOUNCE 0x48
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#define PORTA_EOI 0x4c
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#define EXT_PORTA 0x50
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#define EXT_PORTB 0x54
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#define EXT_PORTC 0x58
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#define EXT_PORTD 0x5c
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#define INT_CLOCK_SYNC 0x60 /* alias LS_SYNC */
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#define VER_ID_CODE 0x6c
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#define CONFIG_REG2 0x70
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#define CONFIG_REG1 0x74
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#define LS_SYNC_POS (0)
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#endif /* ZEPHYR_DRIVERS_GPIO_GPIO_DW_REGISTERS_H_ */
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