2015-11-10 22:13:54 +01:00
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/*gpio_dw_registers.h - Private gpio's registers header*/
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/*
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* Copyright (c) 2015 Intel Corporation.
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*
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2017-01-19 02:01:01 +01:00
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* SPDX-License-Identifier: Apache-2.0
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2015-11-10 22:13:54 +01:00
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*/
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2018-09-14 19:43:44 +02:00
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#ifndef ZEPHYR_DRIVERS_GPIO_GPIO_DW_REGISTERS_H_
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#define ZEPHYR_DRIVERS_GPIO_GPIO_DW_REGISTERS_H_
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2016-11-15 12:39:35 +01:00
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gpio: For ARC EM Starterkit, a 4-port GPIO implementation is being added
The file gpio_dw_registers.h already had the 4-port GPIO
registers defined, yet the gpio_dw.c implementation didn't
support it properly. There are 4 ports here, not 2, and only
PORTA can support interrupts and debounce.
On the em_starterkit board, for example, PORTA
has 3 bits for buttons: A, L and R. The other 3 ports should not
be used with interrupts & debounce.
I've re-worked this file to derive the port number from the
base address given. The lower 6 bits are divided by 12 to
derive the port number. From this, the registers EXT_PORTA,
EXT_PORTB, EXT_PORTC or EXT_PORTD can be read.
Also, for those ports that don't support interrupts,
set irq_num to 0, and that code will be avoided. I've verified
that I can access GPIO now correctly on the EM Starterkit. The
em_starterkit board support will be submitted soon but I'm
staging in this change first.
Change-Id: I98dbe083e03e046b40e07b4b14a99a39a6d0f0be
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-17 06:55:01 +02:00
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/** This definition of GPIO related registers supports four ports: A, B, C, D
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* yet only PORTA supports interrupts and debounce.
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*/
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2015-11-10 22:13:54 +01:00
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#define SWPORTA_DR 0x00
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#define SWPORTA_DDR 0x04
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2016-05-09 22:59:49 +02:00
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#define SWPORTA_CTL 0x08
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2015-11-10 22:13:54 +01:00
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#define SWPORTB_DR 0x0c
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#define SWPORTB_DDR 0x10
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2016-05-09 22:59:49 +02:00
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#define SWPORTB_CTL 0x14
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2015-11-10 22:13:54 +01:00
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#define SWPORTC_DR 0x18
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#define SWPORTC_DDR 0x1c
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2016-05-09 22:59:49 +02:00
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#define SWPORTC_CTL 0x20
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2015-11-10 22:13:54 +01:00
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#define SWPORTD_DR 0x24
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#define SWPORTD_DDR 0x28
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2016-05-09 22:59:49 +02:00
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#define SWPORTD_CTL 0x2c
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2015-11-10 22:13:54 +01:00
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#define INTEN 0x30
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2016-01-20 10:20:07 +01:00
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#define INTMASK 0x34
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2015-11-10 22:13:54 +01:00
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#define INTTYPE_LEVEL 0x38
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#define INT_POLARITY 0x3c
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#define INTSTATUS 0x40
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2016-05-09 22:59:49 +02:00
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#define RAW_INTSTATUS 0x44
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2015-11-10 22:13:54 +01:00
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#define PORTA_DEBOUNCE 0x48
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#define PORTA_EOI 0x4c
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#define EXT_PORTA 0x50
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#define EXT_PORTB 0x54
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#define EXT_PORTC 0x58
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#define EXT_PORTD 0x5c
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2016-05-09 22:59:49 +02:00
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#define INT_CLOCK_SYNC 0x60 /* alias LS_SYNC */
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#define VER_ID_CODE 0x6c
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#define CONFIG_REG2 0x70
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#define CONFIG_REG1 0x74
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2015-12-01 16:00:39 +01:00
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#define LS_SYNC_POS (0)
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2016-11-15 12:39:35 +01:00
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2018-09-14 19:43:44 +02:00
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#endif /* ZEPHYR_DRIVERS_GPIO_GPIO_DW_REGISTERS_H_ */
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