b1cc7312cf
It did not build in x86_64 due to the fact that cr0 is a 64bits register in such architecture, instead of being a 32bits one originaly so the place holder has to follow that size. Such place holder must be initialized to 0 to make sure no upper 32 bits ends up set which would conclude in a general protection error. Operand size specifier (l, q ...) is useless as well in this context. Clearing up the masks by using proper macros. Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
122 lines
2.5 KiB
C
122 lines
2.5 KiB
C
/*
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* Copyright (c) 2013-2014 Wind River Systems, Inc.
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* Copyright (c) 2021 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Cache manipulation
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*
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* This module contains functions for manipulation caches.
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/arch/cpu.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/toolchain.h>
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#include <zephyr/cache.h>
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#include <stdbool.h>
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/* Not Write-through bit */
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#define X86_REG_CR0_NW BIT(29)
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/* Cache Disable bit */
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#define X86_REG_CR0_CD BIT(30)
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static inline void z_x86_wbinvd(void)
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{
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__asm__ volatile("wbinvd;\n\t" : : : "memory");
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}
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void arch_dcache_enable(void)
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{
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unsigned long cr0 = 0;
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/* Enable write-back caching by clearing the NW and CD bits */
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__asm__ volatile("mov %%cr0, %0;\n\t"
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"and %1, %0;\n\t"
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"mov %0, %%cr0;\n\t"
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: "=r" (cr0)
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: "i" (~(X86_REG_CR0_NW | X86_REG_CR0_CD)));
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}
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void arch_dcache_disable(void)
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{
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unsigned long cr0 = 0;
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/* Enter the no-fill mode by setting NW=0 and CD=1 */
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__asm__ volatile("mov %%cr0, %0;\n\t"
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"and %1, %0;\n\t"
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"or %2, %0;\n\t"
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"mov %0, %%cr0;\n\t"
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: "=r" (cr0)
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: "i" (~(X86_REG_CR0_NW)),
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"i" (X86_REG_CR0_CD));
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/* Flush all caches */
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z_x86_wbinvd();
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}
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int arch_dcache_flush_all(void)
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{
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z_x86_wbinvd();
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return 0;
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}
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int arch_dcache_invd_all(void)
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{
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z_x86_wbinvd();
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return 0;
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}
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int arch_dcache_flush_and_invd_all(void)
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{
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z_x86_wbinvd();
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return 0;
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}
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/**
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* No alignment is required for either <virt> or <size>, but since
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* sys_cache_flush() iterates on the cache lines, a cache line alignment for
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* both is optimal.
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*
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* The cache line size is specified via the d-cache-line-size DTS property.
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*/
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int arch_dcache_flush_range(void *start_addr, size_t size)
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{
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size_t line_size = sys_cache_data_line_size_get();
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uintptr_t start = (uintptr_t)start_addr;
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uintptr_t end = start + size;
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if (line_size == 0U) {
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return -ENOTSUP;
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}
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end = ROUND_UP(end, line_size);
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for (; start < end; start += line_size) {
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__asm__ volatile("clflush %0;\n\t" :
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"+m"(*(volatile char *)start));
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}
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#if defined(CONFIG_X86_MFENCE_INSTRUCTION_SUPPORTED)
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__asm__ volatile("mfence;\n\t":::"memory");
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#else
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__asm__ volatile("lock; addl $0,-4(%%esp);\n\t":::"memory", "cc");
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#endif
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return 0;
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}
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int arch_dcache_invd_range(void *start_addr, size_t size)
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{
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return arch_dcache_flush_range(start_addr, size);
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}
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int arch_dcache_flush_and_invd_range(void *start_addr, size_t size)
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{
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return arch_dcache_flush_range(start_addr, size);
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}
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