0369998e61
MIPS (Microprocessor without Interlocked Pipelined Stages) is a instruction set architecture (ISA) developed by MIPS Computer Systems, now MIPS Technologies. This commit provides MIPS architecture support to Zephyr. It is compatible with the MIPS32 Release 1 specification. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
56 lines
1.1 KiB
C
56 lines
1.1 KiB
C
/*
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* Copyright (c) 2020 Antony Pavlov <antonynpavlov@gmail.com>
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*
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* based on arch/riscv/include/kernel_arch_func.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Private kernel definitions
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*
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* This file contains private kernel function/macro definitions and various
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* other definitions for the MIPS processor architecture.
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*/
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#ifndef ZEPHYR_ARCH_MIPS_INCLUDE_KERNEL_ARCH_FUNC_H_
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#define ZEPHYR_ARCH_MIPS_INCLUDE_KERNEL_ARCH_FUNC_H_
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#include <kernel_arch_data.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef _ASMLANGUAGE
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static ALWAYS_INLINE void arch_kernel_init(void)
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{
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}
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static ALWAYS_INLINE void
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arch_thread_return_value_set(struct k_thread *thread, unsigned int value)
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{
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thread->arch.swap_return_value = value;
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}
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FUNC_NORETURN void z_mips_fatal_error(unsigned int reason,
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const z_arch_esf_t *esf);
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static inline bool arch_is_in_isr(void)
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{
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return _current_cpu->nested != 0U;
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}
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#ifdef CONFIG_IRQ_OFFLOAD
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void z_irq_do_offload(void);
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#endif
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* ZEPHYR_ARCH_MIPS_INCLUDE_KERNEL_ARCH_FUNC_H_ */
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