0369998e61
MIPS (Microprocessor without Interlocked Pipelined Stages) is a instruction set architecture (ISA) developed by MIPS Computer Systems, now MIPS Technologies. This commit provides MIPS architecture support to Zephyr. It is compatible with the MIPS32 Release 1 specification. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
55 lines
1.6 KiB
C
55 lines
1.6 KiB
C
/*
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* Copyright (c) 2021 Antony Pavlov <antonynpavlov@gmail.com>
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*
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* based on arch/riscv/core/offsets/offsets.c
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel_arch_data.h>
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#include <gen_offset.h>
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#include <kernel_offsets.h>
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GEN_OFFSET_SYM(_thread_arch_t, swap_return_value);
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GEN_OFFSET_SYM(_callee_saved_t, sp);
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GEN_OFFSET_SYM(_callee_saved_t, s0);
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GEN_OFFSET_SYM(_callee_saved_t, s1);
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GEN_OFFSET_SYM(_callee_saved_t, s2);
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GEN_OFFSET_SYM(_callee_saved_t, s3);
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GEN_OFFSET_SYM(_callee_saved_t, s4);
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GEN_OFFSET_SYM(_callee_saved_t, s5);
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GEN_OFFSET_SYM(_callee_saved_t, s6);
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GEN_OFFSET_SYM(_callee_saved_t, s7);
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GEN_OFFSET_SYM(_callee_saved_t, s8);
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GEN_OFFSET_SYM(z_arch_esf_t, ra);
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GEN_OFFSET_SYM(z_arch_esf_t, gp);
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GEN_OFFSET_SYM(z_arch_esf_t, t0);
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GEN_OFFSET_SYM(z_arch_esf_t, t1);
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GEN_OFFSET_SYM(z_arch_esf_t, t2);
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GEN_OFFSET_SYM(z_arch_esf_t, t3);
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GEN_OFFSET_SYM(z_arch_esf_t, t4);
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GEN_OFFSET_SYM(z_arch_esf_t, t5);
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GEN_OFFSET_SYM(z_arch_esf_t, t6);
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GEN_OFFSET_SYM(z_arch_esf_t, t7);
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GEN_OFFSET_SYM(z_arch_esf_t, t8);
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GEN_OFFSET_SYM(z_arch_esf_t, t9);
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GEN_OFFSET_SYM(z_arch_esf_t, a0);
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GEN_OFFSET_SYM(z_arch_esf_t, a1);
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GEN_OFFSET_SYM(z_arch_esf_t, a2);
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GEN_OFFSET_SYM(z_arch_esf_t, a3);
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GEN_OFFSET_SYM(z_arch_esf_t, v0);
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GEN_OFFSET_SYM(z_arch_esf_t, v1);
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GEN_OFFSET_SYM(z_arch_esf_t, at);
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GEN_OFFSET_SYM(z_arch_esf_t, epc);
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GEN_OFFSET_SYM(z_arch_esf_t, badvaddr);
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GEN_OFFSET_SYM(z_arch_esf_t, hi);
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GEN_OFFSET_SYM(z_arch_esf_t, lo);
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GEN_OFFSET_SYM(z_arch_esf_t, status);
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GEN_OFFSET_SYM(z_arch_esf_t, cause);
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GEN_ABSOLUTE_SYM(__z_arch_esf_t_SIZEOF, STACK_ROUND_UP(sizeof(z_arch_esf_t)));
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GEN_ABS_SYM_END
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