e416c5f1bd
Update current stack limit on every context switch, including switching to irq stack and switching back to thread stack. Signed-off-by: Jaxson Han <jaxson.han@arm.com>
160 lines
3.7 KiB
ArmAsm
160 lines
3.7 KiB
ArmAsm
/*
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* Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* ARM64 Cortex-A ISRs wrapper
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*/
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#include <zephyr/toolchain.h>
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#include <zephyr/linker/sections.h>
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#include <offsets_short.h>
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#include <zephyr/arch/cpu.h>
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#include <zephyr/sw_isr_table.h>
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#include <zephyr/drivers/interrupt_controller/gic.h>
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#include "macro_priv.inc"
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_ASM_FILE_PROLOGUE
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GDATA(_sw_isr_table)
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/*
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* Wrapper around ISRs when inserted in software ISR table
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*
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* When inserted in the vector table, _isr_wrapper() demuxes the ISR table
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* using the running interrupt number as the index, and invokes the registered
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* ISR with its corresponding argument. When returning from the ISR, it
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* determines if a context switch needs to happen.
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*/
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GTEXT(_isr_wrapper)
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SECTION_FUNC(TEXT, _isr_wrapper)
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/* ++_current_cpu->nested to be checked by arch_is_in_isr() */
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get_cpu x0
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ldr w1, [x0, #___cpu_t_nested_OFFSET]
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add w2, w1, #1
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str w2, [x0, #___cpu_t_nested_OFFSET]
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/* If not nested: switch to IRQ stack and save current sp on it. */
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cbnz w1, 1f
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ldr x1, [x0, #___cpu_t_irq_stack_OFFSET]
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mov x2, sp
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mov sp, x1
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str x2, [sp, #-16]!
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#if defined(CONFIG_ARM64_SAFE_EXCEPTION_STACK)
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sub x1, x1, #CONFIG_ISR_STACK_SIZE
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str x1, [x0, #_cpu_offset_to_current_stack_limit]
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#endif
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1:
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#ifdef CONFIG_SCHED_THREAD_USAGE
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bl z_sched_usage_stop
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#endif
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#ifdef CONFIG_TRACING
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bl sys_trace_isr_enter
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#endif
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/* Get active IRQ number from the interrupt controller */
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#if !defined(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER)
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bl arm_gic_get_active
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#else
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bl z_soc_irq_get_active
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#endif /* !CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER */
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#if CONFIG_GIC_VER >= 3
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/*
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* Ignore Special INTIDs 1020..1023 see 2.2.1 of Arm Generic Interrupt Controller
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* Architecture Specification GIC architecture version 3 and version 4
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*/
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cmp x0, 1019
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b.le oob
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cmp x0, 1023
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b.gt oob
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b spurious_continue
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oob:
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#endif
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/* IRQ out of bounds */
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mov x1, #(CONFIG_NUM_IRQS - 1)
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cmp x0, x1
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b.hi spurious_continue
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stp x0, xzr, [sp, #-16]!
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/* Retrieve the interrupt service routine */
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ldr x1, =_sw_isr_table
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add x1, x1, x0, lsl #4 /* table is 16-byte wide */
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ldp x0, x3, [x1] /* arg in x0, ISR in x3 */
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/*
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* Call the ISR. Unmask and mask again the IRQs to support nested
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* exception handlers
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*/
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msr daifclr, #(DAIFCLR_IRQ_BIT)
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blr x3
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msr daifset, #(DAIFSET_IRQ_BIT)
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/* Signal end-of-interrupt */
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ldp x0, xzr, [sp], #16
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spurious_continue:
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#if !defined(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER)
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bl arm_gic_eoi
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#else
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bl z_soc_irq_eoi
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#endif /* !CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER */
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#ifdef CONFIG_TRACING
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bl sys_trace_isr_exit
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#endif
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GTEXT(z_arm64_irq_done)
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z_arm64_irq_done:
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/* if (--_current_cpu->nested != 0) exit */
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get_cpu x0
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ldr w1, [x0, #___cpu_t_nested_OFFSET]
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subs w1, w1, #1
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str w1, [x0, #___cpu_t_nested_OFFSET]
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bne exit
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/* No more nested: retrieve the task's stack. */
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ldr x1, [sp]
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mov sp, x1
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/* retrieve pointer to the current thread */
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ldr x1, [x0, #___cpu_t_current_OFFSET]
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#if defined(CONFIG_ARM64_SAFE_EXCEPTION_STACK)
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/* arch_curr_cpu()->arch.current_stack_limit = thread->arch.stack_limit */
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ldr x2, [x1, #_thread_offset_to_stack_limit]
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str x2, [x0, #_cpu_offset_to_current_stack_limit]
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#endif
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/*
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* Get next thread to schedule with z_get_next_switch_handle().
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* We pass it a NULL as we didn't save the whole thread context yet.
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* If no scheduling is necessary then NULL will be returned.
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*/
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str x1, [sp, #-16]!
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mov x0, xzr
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bl z_get_next_switch_handle
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ldr x1, [sp], #16
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cbz x0, exit
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/*
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* Switch thread
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* x0: new thread
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* x1: old thread
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*/
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bl z_arm64_context_switch
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exit:
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#ifdef CONFIG_STACK_SENTINEL
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bl z_check_stack_sentinel
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#endif
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b z_arm64_exit_exc
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