7904c6f0f3
The exclusive load/store instructions don't work well when MMU and cache are disabled on some cores e.g. Cortex-A72. Change it to voting lock[1] to select the primary core when multi-cores boot simultaneously. The voting lock has reasonable but minimal requirements on the memory system. [1] https://www.kernel.org/doc/html/next/arch/arm/vlocks.html Signed-off-by: Jaxson Han <jaxson.han@arm.com>
28 lines
474 B
C
28 lines
474 B
C
/*
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* Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Definitions for boot code
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*/
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#ifndef _BOOT_H_
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#define _BOOT_H_
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#ifndef _ASMLANGUAGE
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extern void *_vector_table[];
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extern void __start(void);
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#endif /* _ASMLANGUAGE */
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/* Offsets into the boot_params structure */
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#define BOOT_PARAM_MPID_OFFSET 0
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#define BOOT_PARAM_SP_OFFSET 8
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#define BOOT_PARAM_VOTING_OFFSET 16
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#endif /* _BOOT_H_ */
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