| .. |
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andes
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dts: bindings: add andestech,l2c
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2024-04-22 09:19:27 -04:00 |
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efinix
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dts/riscv/efinix: add the efinix,vexriscv-sapphire compatible string
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2024-01-31 10:41:49 +01:00 |
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espressif/esp32c3
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dts: bindings: can: remove optional sample point properties
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2024-03-17 15:36:19 +01:00 |
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gd
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dts/riscv: add riscv compatible string where it's missing
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2024-01-31 10:41:49 +01:00 |
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ite
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ITE: soc: Add the variant of it81302dx
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2024-05-13 11:39:10 +02:00 |
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lowrisc
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dts: opentitan: update plic interrupt count to match spec
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2024-03-22 09:23:46 +00:00 |
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microchip
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dts: mbox: add PolarFire SoC mailbox interface
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2024-02-01 04:33:16 -05:00 |
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niosv
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dts/riscv: add riscv compatible string where it's missing
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2024-01-31 10:41:49 +01:00 |
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nordic
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dts: nordic: Change IRQ number for GPIOTE instances for nRF54L15
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2024-04-25 12:43:58 +00:00 |
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openisa
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dts/riscv/openisa: add compatible strings for the RI5CY cores
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2024-01-31 10:41:49 +01:00 |
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qemu
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dts: set the riscv,isa property for virt-based targets
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2024-05-15 09:30:23 +02:00 |
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sifive
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dts: sifive: Update SoC compats
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2024-04-18 14:56:00 +02:00 |
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starfive
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dts: jh7110: fix memory definitions
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2024-04-09 14:20:39 +02:00 |
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telink
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drivers: intc: plic: define all registers' offset in the driver
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2023-10-04 09:06:28 -04:00 |
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wch
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dts: add the ch32v003 DTSI and bindings
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2024-05-17 19:36:40 +02:00 |
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neorv32.dtsi
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dts/riscv: add riscv compatible string where it's missing
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2024-01-31 10:41:49 +01:00 |
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renode_riscv32_virt.dtsi
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dts: riscv: add a SoC dtsi for Renode RISC-V Virt SoC
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2024-01-08 12:35:10 +01:00 |
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riscv32-litex-vexriscv.dtsi
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dts/riscv/litex: add litex,vexriscv-standard compatible string
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2024-01-31 10:41:49 +01:00 |
