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Filip Kokosinski 0458ac064c dts/riscv/openisa: add compatible strings for the RI5CY cores 
This commits adds two new compatible strings:
* `openisa,ri5cy`
* `openisa,zero-ri5cy`

Adding these two new compats help identify the specific core defined by the
cpu node from the devicetree alone.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2024-01-31 10:41:49 +01:00
..
rv32m1.dtsi dts/riscv/openisa: add compatible strings for the RI5CY cores 2024-01-31 10:41:49 +01:00
rv32m1_ri5cy.dtsi dts: riscv: Remove label property from devicetrees 2022-07-26 12:57:23 -05:00
rv32m1_zero_riscy.dtsi dts: riscv: Remove label property from devicetrees 2022-07-26 12:57:23 -05:00