8db1a5add2
Removing the edge-trigger Kconfig as it is supported by default in the RISCV PLIC specifications. Define the edge-trigger register offset in the driver instead of retrieving the value from devicetree as it is not something configurable. The value 0x1080 is defined in Andes & Telink datasheets. Updated build_all testcase. Signed-off-by: Yong Cong Sin <ycsin@meta.com>
15 lines
314 B
YAML
15 lines
314 B
YAML
# Copyright (c) 2018, SiFive Inc.
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# SPDX-License-Identifier: Apache-2.0
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description: SiFive RISCV-V platform-local interrupt controller
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compatible: "sifive,plic-1.0.0"
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include: riscv,plic0.yaml
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properties:
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riscv,ndev:
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type: int
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description: Number of external interrupts supported
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required: true
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