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Lucas Tamborrino e282b0ea84 soc: esp32xx: refactor clock and RTC subsystems 
The RTC subsystem in espressif's SOCs, among other tasks
is responsible for clock selection for CPU and for low
power domain clocks such as RTC_SLOW and RTC_FAST.

This commit allows for proper clock source and rate
selection for CPU, using the espressif,riscv and
espressif,xtensa-lx6/7 bindings.

It also enables clock selection for RTC_FAST and RTC_SLOW,
that impacts some peripherals, such as rtc_timer.

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2024-05-27 01:37:18 -07:00
..
altr,nios2f.yaml yamllint: indentation: fix dts/bindings/ 2023-01-04 14:23:53 +01:00
andes,andescore-v5.yaml dts/riscv/andes: add andestech,andescore-v5 compatible string 2024-01-31 10:41:49 +01:00
arm,cortex-a53.yaml
arm,cortex-a55.yaml dts: binding: add cortex-a55 dts binding 2022-12-20 09:22:40 +01:00
arm,cortex-a72.yaml
arm,cortex-a76.yaml dts: arm64: Add device tree for Intel SoCFPGA Agilex5 platform 2023-07-25 16:58:01 +00:00
arm,cortex-m.yaml log: swo: enable pin control support for swo log backend 2022-06-28 16:02:09 -05:00
arm,cortex-m0+.yaml
arm,cortex-m0.yaml
arm,cortex-m1.yaml
arm,cortex-m3.yaml
arm,cortex-m4.yaml
arm,cortex-m4f.yaml
arm,cortex-m7.yaml
arm,cortex-m23.yaml
arm,cortex-m33.yaml
arm,cortex-m33f.yaml
arm,cortex-r4.yaml
arm,cortex-r4f.yaml
arm,cortex-r5.yaml
arm,cortex-r5f.yaml
arm,cortex-r7.yaml
arm,cortex-r52.yaml arch: arm: Add support for Cortex-R52 2022-03-11 10:59:48 +01:00
arm,cortex-r82.yaml
cdns,tensilica-xtensa-lx3.yaml dts: cpu: add cdns,tensilica-xtensa-lx3 2023-08-26 16:50:40 -04:00
cdns,tensilica-xtensa-lx4.yaml
cdns,tensilica-xtensa-lx6.yaml yamllint: indentation: fix dts/bindings/ 2023-01-04 14:23:53 +01:00
cdns,tensilica-xtensa-lx7.yaml yamllint: indentation: fix dts/bindings/ 2023-01-04 14:23:53 +01:00
cpu.yaml dts: arm64: Add device tree for Intel SoCFPGA Agilex5 platform 2023-07-25 16:58:01 +00:00
efinix,vexriscv-sapphire.yaml dts/riscv/efinix: add the efinix,vexriscv-sapphire compatible string 2024-01-31 10:41:49 +01:00
espressif,riscv.yaml soc: esp32xx: refactor clock and RTC subsystems 2024-05-27 01:37:18 -07:00
espressif,xtensa-lx6.yaml soc: esp32xx: refactor clock and RTC subsystems 2024-05-27 01:37:18 -07:00
espressif,xtensa-lx7.yaml soc: esp32xx: refactor clock and RTC subsystems 2024-05-27 01:37:18 -07:00
gaisler,leon3.yaml dts: sparc: add cpus node to leon3 2022-01-11 10:46:20 +01:00
intel,alder-lake.yaml dts: bindings: Update compats and filenames 2023-09-28 09:35:16 +02:00
intel,apollo-lake.yaml dts: bindings: Update compats and filenames 2023-09-28 09:35:16 +02:00
intel,elkhart-lake.yaml dts: bindings: Update compats and filenames 2023-09-28 09:35:16 +02:00
intel,ish.yaml boards: x86: Add boards and SoCs for Intel ISH 2023-07-28 17:49:09 +02:00
intel,lakemont.yaml dts: bindings: rename files ending with yml 2022-07-24 17:25:13 -04:00
intel,niosv.yaml dts/riscv: add missing riscv,isa fields and modify existing ones 2023-09-14 14:34:34 +02:00
intel,raptor-lake.yaml dts: bindings: Update compats and filenames 2023-09-28 09:35:16 +02:00
intel,x86.yaml
ite,riscv-ite.yaml dts/riscv: add missing riscv,isa fields and modify existing ones 2023-09-14 14:34:34 +02:00
litex,vexriscv-standard.yaml dts/riscv/litex: add litex,vexriscv-standard compatible string 2024-01-31 10:41:49 +01:00
lowrisc,ibex.yaml dts/riscv/lowrisc: add lowrisc,ibex compatible string 2024-01-31 10:41:49 +01:00
neorv32-cpu.yaml dts/riscv: add missing riscv,isa fields and modify existing ones 2023-09-14 14:34:34 +02:00
nordic,vpr.yaml dts: Add and extend Nordic bindings needed for nRF54H20 2024-02-02 16:40:11 +01:00
nuclei,bumblebee.yaml soc: riscv: gd32vf103: simplify MCAUSE exception mask handling 2024-01-15 09:58:03 +01:00
openisa,ri5cy.yaml dts/riscv/openisa: add compatible strings for the RI5CY cores 2024-01-31 10:41:49 +01:00
openisa,zero-ri5cy.yaml dts/riscv/openisa: add compatible strings for the RI5CY cores 2024-01-31 10:41:49 +01:00
qemu,nios2-zephyr.yaml yamllint: indentation: fix dts/bindings/ 2023-01-04 14:23:53 +01:00
qemu,riscv-virt.yaml dts: set the riscv,isa property for virt-based targets 2024-05-15 09:30:23 +02:00
riscv,cpus.yaml dts/bindings: move RISC-V cores bindings to dts/bindings/cpu/ 2024-01-31 10:41:49 +01:00
sample_controller.yaml
sifive,e24.yaml dts/bindings: move RISC-V cores bindings to dts/bindings/cpu/ 2024-01-31 10:41:49 +01:00
sifive,e31.yaml dts/bindings: move RISC-V cores bindings to dts/bindings/cpu/ 2024-01-31 10:41:49 +01:00
sifive,e51.yaml dts/bindings: move RISC-V cores bindings to dts/bindings/cpu/ 2024-01-31 10:41:49 +01:00
sifive,s7.yaml dts/bindings: move RISC-V cores bindings to dts/bindings/cpu/ 2024-01-31 10:41:49 +01:00
sifive,u54.yaml dts/riscv/microchip: add missing cpu nodes compats in mpfs.dtsi 2024-01-31 10:41:49 +01:00
sifive-common.yaml dts/bindings: move RISC-V cores bindings to dts/bindings/cpu/ 2024-01-31 10:41:49 +01:00
snps,arcem.yaml
telink,b91.yaml dts/riscv: add missing riscv,isa fields and modify existing ones 2023-09-14 14:34:34 +02:00
zephyr,native-posix-cpu.yaml