3aeefd2250
Existing solutions for linking the Xtensa vector table are a
cut-and-paste mess of inherited code, with more than a dozen special
sections that need to be linked into many special MEMORY{} regions.
Accept the existing convention used by C/asm code, but automatically
detect the needed offsets for the platform from core-isa.h (it can
share the preprocessing with gen_zsr.py) and emit a file that can be
included in lieu of all the existing boilerplate.
Signed-off-by: Andy Ross <andyross@google.com>
123 lines
4.8 KiB
Python
Executable file
123 lines
4.8 KiB
Python
Executable file
#!/usr/bin/env python3
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# Copyright 2023 The ChromiumOS Authors
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# SPDX-License-Identifier: Apache-2.0
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import sys
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import re
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# Xtensa Vector Table linker generator
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#
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# Takes a pre-processed (gcc -dM) core-isa.h file as its first
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# argument, and emits a GNU linker section declartion which will
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# correctly load the exception vectors and literals as long as their
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# code is declared using standard conventions (see below).
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#
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# The section name will be ".z_xtensa_vectors", and a symbol
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# "z_xtensa_vecbase" is emitted containing a valid value for the
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# VECBASE SR at runtime.
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#
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# Obviously, this requires that XCHAL_HAVE_VECBASE=1. A similar trick
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# could be played to load vectors at fixed addresses on hardware that
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# lacks VECBASE, but the core-isa.h interface is inexplicably
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# different.
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#
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# Because the "standard conventions" (which descend from somewhere in
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# Cadence) are not documented anywhere and just end up cut and pasted
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# between devices, here's an attempt at a specification:
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#
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# + The six register window exception vectors are defined with offsets
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# internal to their assembly code. They are linked in a single
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# section named ".WindowVectors.text".
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#
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# + The "kernel", "user" and "double exception" vectors are emitted in
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# sections named ".KernelExceptionVector.text",
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# "UserExceptionVector.text" and "DoubleExceptionVector.text"
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# respectively.
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#
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# + XEA2 interrupt vectors are in sections named
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# ".Level<n>InterruptVector.text", except (!) for ones which are
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# given special names. The "debug" and "NMI" interrupts (if they
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# exist) are technically implemented as standard interrupt vectors
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# (of a platform-dependent level), but the code for them is emitted
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# in ".DebugExceptionVector.text" and ".NMIExceptionVector.text",
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# and not a section corresponding to their interrupt level.
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#
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# + Any unused bytes at the end of a vector are made available as
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# storage for immediate values used by the following vector (Xtensa
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# can only back-reference immediates for MOVI/L32R instructions) as
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# a "<name>Vector.literal" section. Note that there is no guarantee
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# of how much space is available, it depends on the previous
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# vector's code size. Zephyr code has historically not used this
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# space, as support in existing linker scripts is inconsistent. But
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# it's exposed here.
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coreisa = sys.argv[1]
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debug_level = 0
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# Translation for the core-isa.h vs. linker section naming conventions
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sect_names = { "DOUBLEEXC" : "DoubleException",
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"KERNEL" : "KernelException",
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"NMI" : "NMIException",
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"USER" : "UserException" }
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offsets = {}
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with open(coreisa) as infile:
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for line in infile.readlines():
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m = re.match(r"^#define\s+XCHAL_([^ ]+)_VECOFS\s*(.*)", line.rstrip())
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if m:
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(sym, val) = (m.group(1), m.group(2))
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if sym == "WINDOW_OF4":
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# This must be the start of the section
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assert eval(val) == 0
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elif sym.startswith("WINDOW"):
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# Ignore the other window exceptions, they're internally sorted
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pass
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elif sym == "RESET":
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# Ignore, not actually part of the vector table
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pass
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elif sym == "DEBUG":
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# This one is a recursive macro that doesn't expand,
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# so handle manually
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m = re.match(r"XCHAL_INTLEVEL(\d+)_VECOFS", val)
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if not m:
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print(f"no intlevel match for debug val {val}")
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assert m
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debug_level = eval(m.group(1))
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else:
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if val == "XCHAL_NMI_VECOFS":
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# This gets recursively defined in the other
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# direction, so ignore the INTLEVEL
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pass
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else:
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addr = eval(val)
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m = re.match(r"^INTLEVEL(\d+)", sym)
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if m:
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offsets[f"Level{m.group(1)}Interrupt"] = addr
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else:
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offsets[sect_names[sym]] = addr
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if debug_level > 0:
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old = f"Level{debug_level}Interrupt"
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offsets[f"DebugException"] = offsets[old]
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del offsets[old]
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sects = list(offsets)
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sects.sort(key=lambda s: offsets[s])
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print("/* Automatically Generated Code - Do Not Edit */")
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print("/* See arch/xtensa/core/gen_vector.py */")
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print("")
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# The 1k alignment is experimental, the docs on the Relocatable Vector
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# Option doesn't specify an alignment at all, but writes to the
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# bottom bits don't take...
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print( " .z_xtensa_vectors : ALIGN(1024) {")
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print( " z_xtensa_vecbase = .;")
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print(f" KEEP(*(.WindowVectors.text));")
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for s in sects:
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print(f" KEEP(*(.{s}Vector.literal));")
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print( " . = 0x%3.3x;" % (offsets[s]))
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print(f" KEEP(*(.{s}Vector.text));")
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print(" }")
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