Embeds both an anonymous union and an anonymous structure within the
k_spinlock structure to ensure that the structure can easily have a
non-zero size.
This new option provides a cleaner way to specify that the
spinlock structure must have a non-zero size. A non-zero size
is necessary when C++ support is enabled, or when a library
or application wants to create an array of spinlocks.
Fixes#59922
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
Add OTP driver for the SiFli SF32LB series eFuse controller.
This driver provides read-only access to the eFuse OTP memory
with the following features:
- Cache mechanism: all eFuse content is loaded into RAM during
initialization for improved read performance
- Support for 4 banks x 32 bytes = 128 bytes total OTP storage
- LDO voltage adjustment before reading as required by hardware
Signed-off-by: Haoran Jiang <halfsweet@halfsweet.cn>
Add devicetree binding for the SiFli SF32LB series eFuse OTP memory
controller. The eFuse provides 128 bytes (4 banks x 32 bytes) of
one-time programmable storage.
Signed-off-by: Haoran Jiang <halfsweet@halfsweet.cn>
The base address was written to an incorrect register, which caused
incorrect data to be read from the I2C target. This has been fixed by
writing to the correct register.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
next_event should not be global. This can cause
linkage conflicts if another file defines a symbol
with the same name.
Signed-off-by: Flavio Ceolin <flavio@hubblenetwork.com>
Fix macros/symbols that broke after changes were merged to get the
absolute address through ranges property
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Fix inconsistent macro name from IOMUX_GET_SCTIMER_IN_CLR_ENABLE
to IOMUX_GET_CTIMER_CLR_ENABLE to align with the actual CTimer
functionality and related macro naming convention.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Correct GIC addresses to match ARM Cortex-R8 TRM PERIPHBASE specification.
GIC must be at fixed offsets from PERIPHBASE (0xAE000000)
- Distributor: 0xAE001000 (PERIPHBASE + 0x1000)
- CPU Interface: 0xAE000100 (PERIPHBASE + 0x100)
Updated device tree, MPU regions, and Renode configuration to use
correct addresses and add required memory protection.
Signed-off-by: Raja Shahzaib <rshahzaib077@gmail.com>
Commit f55358bcbf changed all hex values to
use lowercase characters. Update the test accordingly.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Correct a clock initialization ordering issue where IMO, an internal
high speed oscillator, was being setup before ILO. This does not match
the MTB initialization order and would cause the part to fault.
Sets up the default clock configuration on the part to be 48MHz. Adjusts
the default WCO (low speed external crystal source) to be 32768 as the
eval board has this crystal on it. Enables common clock elements
(hf_clk, clock_pump) as needed in the part dts rather than the board.
Signed-off-by: Braeden Lane <Braeden.Lane@infineon.com>
The actual_velocity pointer is dereferenced unconditionally before
the NULL check, making the conditional LOG_DBG() guard ineffective.
Since actual_velocity must be valid to reach this point, the
conditional check is redundant and misleading.
Remove it and log the value unconditionally to reflect the actual
control flow.
Signed-off-by: Gaetan Perrot <gaetan.perrot@spacecubics.com>
Remove a dead error check which check ret but ret wasn't even
assigned before the test.
Remove the useless condition to make the intent explicit and clean
up the code.
Signed-off-by: Gaetan Perrot <gaetan.perrot@spacecubics.com>
Correct a clock initialization ordering issue where IMO, an internal
high speed oscillator, was being setup before ILO. This does not match
the MTB initialization order and would cause the part to fault.
Sets up the default clock configuration on the part to be 48MHz. Adjusts
the default WCO (low speed external crystal source) to be 32768 as the
eval board has this crystal on it. Enables common clock elements
(hf_clk, clock_pump) as needed in the part dts rather than the board.
Signed-off-by: Tom Burdick <thomas.burdick@infineon.com>
The GPIO interrupts were incorrectly set to priority 4 on an m0 with
only 4 priorities, max is 3. Several of the gpio ports were missing
their interrupt property as it is a shared interrupt number but the
driver seems to account for this. Added the missing interrupt property
on these ports.
Signed-off-by: Tom Burdick <thomas.burdick@infineon.com>
According to the manual, device should wait:
AT+QPOWD=1
OK
POWERED DOWN
before shutting down. This should take about 300 ms.
Correct the timing to match BG96 manual, where power_key pulse
is 500ms (on a shut down, it say 650ms).
The start-up time of UART is described as >=4900ms so start_ms
is now set to 5s. It does not require 10s.
We require more than 100ms to reset from CMUX to AT mode UART,
500ms seems to be enough. Manual does not describe this delay.
Shutdown time is described as 2s, but we don't typically use that
as the shutdown script receives the POWERED DOWN message and is now
faster.
Signed-off-by: Seppo Takalo <seppo.takalo@nordicsemi.no>
When net_if_down() is called, the PPP_DEAD event is handled
in state machine before the modem_ppp_ppp_api_stop()
requests the driver to suspend.
Prevent non-wanted re-dial script by checking the admin
state (UP/DOWN) of the PPP interface, before dealing with
lost connection.
Signed-off-by: Seppo Takalo <seppo.takalo@nordicsemi.no>
GPIO polarity and pull configuration were incorrect for the hardware.
Button shorts to ground and requires pull-up with active-low logic.
LED is active-low per schematic. These changes allow the button sample
to work correctly on this board.
Fixeszephyrproject-rtos/zephyr#103342
Signed-off-by: Elkana Molson <elkanamol@gmail.com>
We changed the hardware node name of the QMSPI controller
to be consistent on MEC172x with MEC174x/5x, etc. We updated
two samples using the old name.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
We added the Microchip mec_assy6941 and mec172xevb_assy6906 to the common
flash driver test. We use the SPI_NOR flash driver with the Microchip
XEC QMSPI-LDMA driver. The EVB has a SPI dongle attached with a Winbond
W25Q128JV 16 megabit SPI flash. We changed the name of QMSPI DT hardware
node to match the name at chip level.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
We converted the QMSPI-LDMA driver to linux style with a local
register header in the driver folder. This is part of the long
term plan to remove the MEC5 HAL and have common drivers for
as many SoC's as possible. QMSPI register definitions are in
the SoC layer to be shared with other drivers (MSPI). The driver
was also updated based on changes in the SPI config structure.
The lastest SPI config structure changes force hardware controlled
chip selects and GPIO controlled chip selects to be mutually exclusive.
NOTE: driver works with the flash driver sample
and passes the common flash driver test.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
We updated the SoC Microchip MEC common helper and headers.
Add helper routines to manipulate PCR sleep enable bits, etc.
Add miscellaneous helper routines.
Add QMSPI register definitions to be used by SPI and MSPI drivers.
Create a common header containing includes of all other
common headers to prevent changing each chip's soc.h
Note, we must add build logic to handle naming difference of eSPI
SAF/TAF nodes. Intel changed name of SAF to TAF. MEC15xx and MEC172x
older driver still use SAF in DT node naming.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Before that commit spi was not available for the soc sy1xx.
With this commit a basic usage of spi is possible.
Signed-off-by: Sven Ginka <s.ginka@sensry.de>
Co-authored-by: Fin Maaß <f.maass@vogl-electronic.com>
CoAP response code 2.00 is not defined anywhere in the spec nor
assigned in the IANA registry, therefore it should not be defined
in Zephyr either. Remove the invalid response code and its usage
in tests.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
This change adds optional reset via GPIO support to u-blox M8 driver.
This is useful if host is reset separately from the u-blox M8 GNSS
receiver.
Signed-off-by: Vytautas Virvičius <vytautas@virvicius.dev>
reg attribute is supposed to hold start address and size
instead of start address and end address. This caused
a crash in malloc_prepare().
Signed-off-by: Damian Krolik <damian.krolik@nordicsemi.no>
The out-div binding was removed as dts setting now aligns
literal value, not register value. This commit updates
the out-div node entry to be the literal values as the
translation is now handled in the driver.
Signed-off-by: David Jewsbury <david.jewsbury@nordicsemi.no>
The out_div dts setting differs to the register setting
causing the frequency calcuation to be incorrect.
This was originally intended to be fixed in NRFX but
this requires further investigation on how to approach
translation of literal values to enums in NRFX. This PR
adds a helper function for the conversion for now and
changes the devicetree bindings to align with the literal
value.
Signed-off-by: David Jewsbury <david.jewsbury@nordicsemi.no>
Timer test fail to build with the error below:
.../tick_timer_train.c:12: error: "TIMERS" redefined [-Werror]
12 | #define TIMERS 4
|
In file included from .../zephyr/soc/.../siwg917/soc.h:8,
from .../modules/cmsis_6/cmsis_core_m.h:24,
from .../modules/cmsis_6/cmsis_core.h:10,
from .../zephyr/include/.../asm_inline_gcc.h:24,
from .../zephyr/include/.../asm_inline.h:18,
from .../zephyr/include/.../arch.h:30,
from .../zephyr/include/.../cpu.h:19,
from .../zephyr/include/.../kernel_includes.h:36,
from .../zephyr/include/.../kernel.h:17,
from .../zephyr/tests/.../tick_timer_train.c:7:
.../modules/hal/silabs/wiseconnect/components/.../si91x_device.h:15930:
note: this is the location of the previous definition
Indeed, the CMSIS interface of Silabs siwx91x also defines "TIMERS" symbol.
"TIMERS" is a common names in the CMSIS interfaces. So, it makes sense to
avoid to redefine it in the applications.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Since Zephyr no longer uses deprecated APIs, we no longer need to
disable deprecation warnings.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Let's get rid of deprecated sl_wifi_set_callback. The new
sl_wifi_set_callback_v2 changes the callback prototypes, but they kept the
semantic.
We also take this opportunity to slightly clean up the prototupes of the
callbacks.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
sl_wifi_performance_profile_t is deprecated. The migration to
sl_wifi_performance_profile_v2_t is pretty easy, so there is not reason to
delay it (in fact, the two versions only differ in binary compatibility,
the API is still compatible).
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
sli_save_ap_configuration() and sli_get_saved_ap_configuration() have been
renamed respectively in sli_wifi_save_ap_configuration() and
sli_wifi_get_saved_ap_configuration().
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
