Commit graph

136,983 commits

Author SHA1 Message Date
Silesh C V
f6314e9a43 drivers: pinctrl: add alif pinctrl driver
Add pin control driver for Alif SoCs. The driver manages
pin muxing (alternate function selection) and pad configuration
for Alif SoCs.

Signed-off-by: Silesh C V <silesh@alifsemi.com>
2026-02-17 10:31:21 +01:00
Silesh C V
4ed4684d57 dts: bindings: pinctrl: add alif pinctrl bindings
Add device tree bindings for the Alif Semiconductor pin controller
and Ensemble SoC specific pin definitions.

The binding supports pin multiplexing via predefined macros that
encode port, pin, and alternate function into a 32-bit value.
Pad configuration (input enable, drive strength, slew rate, bias
control, etc.) is specified using standard pinctrl properties.

Signed-off-by: Silesh C V <silesh@alifsemi.com>
2026-02-17 10:31:21 +01:00
Silesh C V
d5488b5395 drivers: clock_control: add alif clock driver
Add clock control driver for Alif Semiconductor SoCs. The driver
manages peripheral clocks in the device by operating on multiple
discontiguous register regions (called modules in this driver).
In this initial version, the driver supports on, off, get_rate and
get_status API.

Co-authored-by: Manoj A Murudi <manoj.murudi@alifsemi.com>
Signed-off-by: Silesh C V <silesh@alifsemi.com>
2026-02-17 10:31:21 +01:00
Silesh C V
c1a848d4fb dts: arm: alif: ensemble: add clock controller node
Add the clock controller node for the Ensemble family.

Signed-off-by: Silesh C V <silesh@alifsemi.com>
2026-02-17 10:31:21 +01:00
Silesh C V
83afd9b880 dts: bindings: clock: add alif clock controller binding
Add devicetree binding for the Alif Semiconductor clock controller.
The clock controller manages peripheral clocks using registers spread
across multiple discontiguous regions (called clock modules in the
binding and driver).

Clock specifiers use a single cell containing an encoded clock ID
that packs module, register offset, clock enable information and
source clock information.

Co-authored-by: Manoj A Murudi <manoj.murudi@alifsemi.com>
Signed-off-by: Silesh C V <silesh@alifsemi.com>
2026-02-17 10:31:21 +01:00
Silesh C V
0cdd41ff7c dts: arm: alif: ensemble: add fixed root clocks
Add fixed-clock nodes for some of the Ensemble family root clocks.
These clocks serve as input sources for peripheral clocks managed
by the clock controller.

Signed-off-by: Silesh C V <silesh@alifsemi.com>
2026-02-17 10:31:21 +01:00
Silesh C V
448b24f1de dt-bindings: clock: add alif clock bindings
Alif SoCs organize clock control into multiple register regions
(called clock modules in the driver). Bitfields in these modules
are used to manage different clocks in the SoC. Add headers that
define the encoding of the information necessary to operate on
the clocks.

The encoding packs clock control information into a single 32-bit
value that includes clock module and register offset within the
module, clock enable information and clock source information.

Note that alif-clocks-common.h contains the common encoding scheme,
module definitions etc. that could be reused by other Alif SoCs and
alif-ensemble-clocks.h defines the peripheral clock IDs specific to
the Ensemble family (UART 0-7 clocks are added for initial support).

Co-authored-by: Manoj A Murudi <manoj.murudi@alifsemi.com>
Signed-off-by: Silesh C V <silesh@alifsemi.com>
2026-02-17 10:31:21 +01:00
Silesh C V
79585731cc dts: arm: alif: ensemble: add peripheral mpu region
The Ensemble SoCs have a peripheral region at 0x1A000000 (8 MB)
that hosts peripherals such as pinmux and clock control registers.
This deviates from the standard Cortex-M memory map and requires
explicit MPU configuration with device memory attributes.

Signed-off-by: Silesh C V <silesh@alifsemi.com>
2026-02-17 10:31:21 +01:00
Silesh C V
cd174cc910 soc: alif: introduce Ensemble family and E8 series
Ensemble is a family of processors from Alif Semiconductor
targeted at low-end to high-end intelligent IoT endpoint
applications. Series (E1-E8) within the family scale up from
single-core MCUs to quad-core MCU/MPU fusion processors.

Add support for the Ensemble family and the E8 series with the
AE822FA0E5597LS0 SoC. The SoC contains two Cortex-M55 cores: one
configured to maximize power efficiency (RTSS-HE - High Efficiency
Real Time Subsystem) and the other to maximize compute performance
(RTSS-HP - High Performance Real Time Subsystem).

Link: https://alifsemi.com/products/ensemble/
Link: https://alifsemi.com/products/ensemblegenai/
Link: https://alifsemi.com/ensemble-e8-series/

Co-authored-by: Tanay Rami <tanay@alifsemi.com>
Co-authored-by: Prabhakar Kumar <prabhakar.kumar@alifsemi.com>
Signed-off-by: Silesh C V <silesh@alifsemi.com>
2026-02-17 10:31:21 +01:00
Silesh C V
67df80530d dts: arm: alif: ensemble: add RTSS-HE and RTSS-HP subsystems
The Alif Ensemble family of processors contains up to two
Cortex-M55 cores, each optimized for different use cases. One
configured to maximize power efficiency and the other to maximize
compute performance. These are called the High Efficiency Real Time
Subsystem (RTSS-HE) and the High Performance Real Time Subsystem
(RTSS-HP) respectively.

Add the device tree include files for these subsystems with their
CPU, MPU and TCM definitions.

Signed-off-by: Silesh C V <silesh@alifsemi.com>
2026-02-17 10:31:21 +01:00
Silesh C V
2d90e42160 dts: bindings: vendor-prefixes: add alif prefix
Add prefix for Alif Semiconductor.

Signed-off-by: Silesh C V <silesh@alifsemi.com>
2026-02-17 10:31:21 +01:00
Emil Gydesen
309b5b3c01 Bluetooth: CAP: Add ep conn check in unicast audio start
Add check in valid_unicast_audio_start_param to verify
that the ep connection matches the member_conn.

Instead of declaring the endpoints in the unit tests, we
not define them in the mock unicast client and use the
discover function to get pointers.

This allows for a proper implementation of
bt_bap_unicast_client_has_ep as well as makes the tests more similar
to a normal application.

This change required a significant change in the unicast_stop
unit tests as well, which uncovered a small bug in the implementation.
The bug was fixed as part of this commit.

Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
2026-02-17 10:31:09 +01:00
Fabio Baltieri
0006806b3f bindings: pic32cz-ca-dpll: drop compatible from child child
Same as 17a91d84e4 but for the child of the child, missed it on the
first patch.

Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
2026-02-17 10:30:55 +01:00
Aksel Skauge Mellbye
8e6c936e3e tests: drivers: pwm: Enable tests on xg24_rb4187c
Enable PWM tests on xg24_rb4187c.

Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
2026-02-16 21:22:29 +00:00
Fabrice DJIATSA
a28f4fb3a5 samples: drivers: memc: use log function instead of printk
Changed printk() to LOG_INF() to reduce execution time.
This optimization is necessary when using large buffers, such
as on the STM32H7S_DK with 32 MB of PSRAM. Otherwise, in CI,
the test will fail due to a timeout (60s) occurring before the
test completes its execution and misses printing the required
regex word for the test to be successful.

Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
2026-02-16 21:22:16 +00:00
Jukka Rissanen
3689e05a04 MAINTAINERS: Add esp_hosted wifi driver to be Espressif maintained
The esp_hosted wifi driver is added as a sub-group to Espressif
platform.

Signed-off-by: Jukka Rissanen <jukka.rissanen@nordicsemi.no>
2026-02-16 21:22:05 +00:00
Fabio Baltieri
17a91d84e4 bindings: pic32cz-ca-dpll: drop compatible from child
The child node does not need a compatible, the child properties are
inferred from the partent binding, plus this compatible is confusing the
documentation, which is failing with:

src/boards/microchip/pic32c/pic32cz_ca80_cult/doc/index.rst:36:
WARNING: 'dtcompatible' reference target not found:
microchip,pic32cz-ca-dpllchild [ref.dtcompatible]
1417

Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
2026-02-16 21:21:56 +00:00
Farsin Nasar V A
5d3670bc87 tests: drivers: uart: update testcase.yaml
ensure async extra config applies only to SAME54

Signed-off-by: Farsin Nasar V A <farsin.nasarva@microchip.com>
2026-02-16 16:27:49 +00:00
Dawid Niedzwiecki
2458dc63d9 retained_mem: ram: change initialization level to PRE_KERNEL_1
Change the initialization level of retained_mem RAM driver to
PRE_KERNEL_1.

It allows using the drivers in the pre-kernel stage, which can be a case
for some applications.

Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
2026-02-16 16:27:38 +00:00
Johan Hedberg
3b97f6a1f1 doc: migration-guide-4.4: Mention k_poll change for Bluetooth
Mention that the Bluetooth Host no longer selects POLL, since this may
cause unexpected build issues for applications (it certainly did that for
several in-tree samples).

Signed-off-by: Johan Hedberg <johan.hedberg@silabs.com>
2026-02-16 09:03:09 -06:00
Johan Hedberg
dd37a250b1 Bluetooth: Host: Remove leftover k_poll related code
There's no use of k_poll in the host stack anymore, so remove leftovers
and related definitions.

Signed-off-by: Johan Hedberg <johan.hedberg@silabs.com>
2026-02-16 09:03:09 -06:00
Johan Hedberg
898679e896 Bluetooth: samples: Add missing CONFIG_POLL dependency
A bunch of samples were relying on the Bluetooth host to select POLL,
however since the sample code itself uses k_poll the right thing to do is
to have the samples explicitly enable this feature.

Signed-off-by: Johan Hedberg <johan.hedberg@silabs.com>
2026-02-16 09:03:09 -06:00
Johan Hedberg
39a428c5d9 Bluetooth: Mesh: Add missing select for POLL
The Bluetooth Mesh code depends on k_poll, so it should have the
appropriate select statement in its Kconfig.

Signed-off-by: Johan Hedberg <johan.hedberg@silabs.com>
2026-02-16 09:03:09 -06:00
Robert Robinson
ab374580f2 snippets: nordic: flpr: Define flpr snippet for nRF7120
This commit adds a snippet for the nRF7120 FLPR, to define
memory allocations for flpr core.

Signed-off-by: Robert Robinson <robert.robinson@nordicsemi.no>
2026-02-16 09:02:34 -06:00
Robert Robinson
914c96c663 boards: nordic: nrf7120dk: Align button and led GPIOs with DK
led and button values for nRF7120 had previously been defined
arbitrarily, this commit updates the values to match expected values.

Signed-off-by: Robert Robinson <robert.robinson@nordicsemi.no>
2026-02-16 09:02:34 -06:00
Robert Robinson
83466b2378 boards: nordic: nrf7120dk: Set entropy to PSA RNG as default for ns builds
Non secure applictions can not access cracen directly and must use
PSA API calls instead, therefore default entropy source for non secure
builds must be PSA.

Signed-off-by: Robert Robinson <robert.robinson@nordicsemi.no>
2026-02-16 09:02:34 -06:00
Robert Robinson
7eded43c3d dts: arm: nordic: Disable psa_rng since not default entropy for nRF7120
rng node is the default entropy source for nRF7120, so psa_rng should
be disabled by default.

Signed-off-by: Robert Robinson <robert.robinson@nordicsemi.no>
2026-02-16 09:02:34 -06:00
Robert Robinson
54d9069522 soc/Kconfig: Create a config for nRF71 series soc compatible
SOC_COMPATIBLE_NRF7120_ENGA was erroneously being used in
KConfig filter and therefore not being applied, since soc configs are
generated at compile time. Created SOC_COMPATIBLE_NRF71 to be used at
KConfig build stage.

Signed-off-by: Robert Robinson <robert.robinson@nordicsemi.no>
2026-02-16 09:02:34 -06:00
Robert Robinson
ec3b856c2f dts: nordic: nrf7120: Update MRAM partitions
MRAM sizes were wrongly defined in .dtsi files and
so required updating.

Signed-off-by: Robert Robinson <robert.robinson@nordicsemi.no>
2026-02-16 09:02:34 -06:00
Robert Robinson
1c4c1444fe dts: nordic: nRF7120: Add missing power register in dtsi
Power register was missing from nrf7120_enga.dtsi, this commit
includes it.

Signed-off-by: Robert Robinson <robert.robinson@nordicsemi.no>
2026-02-16 09:02:34 -06:00
Harpreet Saini
1f42f81fb3 drivers: rtc: add driver for DS1302 rtc
Add driver support for maxim DS1302 rtc working in half duplex spi
mode.

Signed-off-by: Harpreet Saini <sainiharpreet29@yahoo.com>
2026-02-16 09:01:49 -06:00
Daniel Leung
098f61700f west: sign/rimage: do not assume SOF source exists
After the removal of the SOF module from the manifest, we should
no longer assume SOF source is available in the signing script.
If SOF source directory does not exist, we point the rimage
config directory to the support directory inside board directory
so that we can use local file to sign images.

Note that with this change, pulling SOF via Zephyr manifest is
no longer supported. Only SOF pulling in Zephyr via manifest is
supported.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2026-02-16 09:01:09 -06:00
Daniel Leung
a4c37560d5 west: sign/rimage: remove --no-manifest workaround
The --no-manifest option is no longer being used so we remove
the workaround.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2026-02-16 09:01:09 -06:00
Anas Nashif
dbd231853d west: sign: use local signing key if specified
Environment variable RIMAGE_SIGN_KEY can be used to specify
the signing key for rimage. We should check if it points
directly to the key instead of always prefixing it with SOF
path.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2026-02-16 09:01:09 -06:00
Daniel Leung
3d46072e91 boards: intel_adsp: add support files for image signing
This adds a few TOML file to support image signing when SOF
source directory is not found, pending changes to the west
signing script. This should allow us to run Zephyr tests on
the device without the need to pull in the whole SOF source
just for a few files.

The files are either copied directly from SOF project
(https://github.com/thesofproject/sof.git) or generated
from build.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2026-02-16 09:01:09 -06:00
Paul He
a14a5b2d60 llext: remove leading -D from CMakeLists.txt
Any leading -D passed to target_compile_definitions on an item will
be removed, here remove them to make code style consistent.

Signed-off-by: Paul He <pawpawhe@gmail.com>
2026-02-16 09:00:09 -06:00
Paul He
0268de24db soc: ti: remove leading -D from CMakeLists.txt
Any leading -D passed to target_compile_definitions on an item will
be removed, here remove them to make code style consistent.

Signed-off-by: Paul He <pawpawhe@gmail.com>
2026-02-16 09:00:09 -06:00
Paul He
6ccdc2d824 modules: openthread: remove leading -D from CMakeLists.txt
Any leading -D passed to target_compile_definitions on an item will
be removed, here remove them to make code style consistent.

Signed-off-by: Paul He <pawpawhe@gmail.com>
2026-02-16 09:00:09 -06:00
Paul He
56e5d47c32 modules: hal_rpi_pico: remove leading -D from CMakeLists.txt
Any leading -D passed to target_compile_definitions on an item will
be removed, here remove them to make code style consistent.

Signed-off-by: Paul He <pawpawhe@gmail.com>
2026-02-16 09:00:09 -06:00
Paul He
bdce342603 lib: posix: remove leading -D from CMakeLists.txt
Any leading -D passed to target_compile_definitions on an item will
be removed, here remove them to make code style consistent.

Signed-off-by: Paul He <pawpawhe@gmail.com>
2026-02-16 09:00:09 -06:00
Sunil Abraham
7b43e13879 boards: microchip: PIC32CZ_CA: configure clock source and frequency
Configure CPU clock using DPLL, sourced from XOSC to achieve 240Mhz.

Signed-off-by: Sunil Abraham <sunil.abraham@microchip.com>
2026-02-16 08:59:23 -06:00
Sunil Abraham
8c2c58de6a drivers: clock_control: PIC32CZ_CA: Add clock control driver
Add clock control driver
Implement bootup clock initialization, on, off, configure and get_rate API

Signed-off-by: Sunil Abraham <sunil.abraham@microchip.com>
2026-02-16 08:59:23 -06:00
Sunil Abraham
7136b03f30 dts: clock: PIC32CZ_CA: Add clock control driver bindings
Add bindings for dfll, dpll, gclk generator, mclk cpu, osc32k, rtc clock
and xosc.

Signed-off-by: Sunil Abraham <sunil.abraham@microchip.com>
2026-02-16 08:59:23 -06:00
Roman Leonov
c32c2d9935 drivers: usb: common: Added host register set for DWC2 controller
Added register bitmask description with low-level abstraction

Signed-off-by: Roman Leonov <jam_roma@yahoo.com>
Co-authored-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
2026-02-16 08:57:09 -06:00
Gokul Rajaram A
8c8ccbdba4 drivers: sensor: ti: tmp1075: add default values to dt binding
The TMP1075 binding defined conversion-rate and
consecutive-fault-measurements as optional properties with no
default values, causing build failures when they were omitted
from the devicetree node.

Add default values matching the hardware reset values from the
datasheet to fix the build failure.

Fixes #100362

Signed-off-by: Gokul Rajaram A <rajaramgokul25@gmail.com>
2026-02-16 08:56:30 -06:00
Henrik Brix Andersen
28cd602a81 scripts: requirements-actions: regen pinned dependencies
Run uv pip compile to get updated hashes for tomli.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2026-02-16 13:03:26 +01:00
Ryan Erickson
889b9cd3dc drivers: can: tcan4x5x: init should call pm_device_driver_init
The final call in the driver init should be pm_device_driver_init.
This ensures the device transitions to active when the driver starts.

Signed-off-by: Ryan Erickson <ryan.erickson@ezurio.com>
2026-02-16 12:53:27 +01:00
Etienne Carriere
79ef2abdaf boards: weact: mini_stm32h7b0: correct slot0 partition size
MiniSTM32H7B0 external NOR flash is 64Mbits large hence 8MBytes.
Correct slot0_parition size from 64MByte to 8Mbyte.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
2026-02-16 12:53:14 +01:00
Allen Zhang
d21cefc7a1 soc: mcxw70: add image length at vector table offset 0x20
Add image length field at vector table offset 0x20

Signed-off-by: Allen Zhang <chunfeng.zhang@nxp.com>
2026-02-16 12:53:00 +01:00
Jukka Rissanen
e791578eef drivers: wifi: simplelink: Deprecating the driver
This offloaded wifi driver is deprecated and will be removed
in a future release. It is currently scheduled to be removed in
Zephyr 4.6. The reason for deprecation is that there is no
maintainer for this driver.

Signed-off-by: Jukka Rissanen <jukka.rissanen@nordicsemi.no>
2026-02-16 12:52:48 +01:00