bt_pacs_register would assert if e.g.
CONFIG_BT_PAC_SRC_NOTIFIABLE=y but param.src_pac = false.
Add checks for setting the attributes, only if the parameter
actually enables the characteristics.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
Replace hardcoded -Wno-misleading-indentation flag with the new
warning_no_misleading_indentation compiler property for both C and C++
compilation in imx91 and imx943 SoCs. This ensures compiler-agnostic
handling of misleading indentation warnings.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Add a new compiler property warning_no_misleading_indentation to allow
disabling misleading indentation warnings. This is implemented for GCC
with the -Wno-misleading-indentation flag.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
After the switch to the native_sim board instead of
the unit_testing board, we no longer need or use these
mocks.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
Enable the sharp MIP display present on the MAX32666EVKIT, using the
bitbang SPI driver, since the hardware SPI peripheral does not support LSB
transfers used by the LS0XX driver.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
Update Meta-IRQ sample README to use `zephyr:code-sample` directive and
standardize "Meta-IRQ" naming.
Fixeszephyrproject-rtos/zephyr#104002
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Ensures this sample is properly cross-referencing the Doxygen API group
it's demonstrating.
Also fix wording of the sample title to align with guidelines
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Define IFX_SCB_ARRAY_SIZE for PSoC Edge SoCs to properly
determine the SCB array size.
Without this change, the driver fails to compile on
PSoC Edge platforms
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
Fix trailing commas in ADVANCED_SPI_FIELDS macro definition
and its usage to ensure clean macro expansion.
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
Get rid of per board CONFIG_HEAP_MEM_POOL_SIZE. The heap mem
pool size is now set globally within the sample Kconfig itself.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Add a requirement of a default 65536 bytes of HEAP in order to be
able to allocate memory for drawing the rectangles of the sample.
Considering that by default the sample is drawing rectangles which
are 1/4 of the display width and have a ratio twice width vs height,
such size should allow to run the sample up to display of 1024 pixel
wide in RGB565 pixel format.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Simplify error handling by having all exit point at same place
and avoid having too many #ifdef statements in the sample.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Add device tree overlays for ADC samples and tests on
CY8CKIT-041S-MAX and CY8CPROTO-041TP boards.
Configures ADC channels with pinctrl for analog inputs on
available header pins. Includes single-ended and differential
channel configurations demonstrating various ADC features.
Added overlays for:
- samples/drivers/adc/adc_dt
- samples/drivers/adc/adc_sequence
- tests/drivers/adc/adc_api
- tests/drivers/adc/adc_error_cases
Signed-off-by: Braeden Lane <Braeden.Lane@infineon.com>
Co-authored-by: Deepika R <deepika@aerlync.com>
Co-authored-by: Sayooj K Karun <sayooj@aerlync.com>
Enable the SAR ADC peripheral on CY8CKIT-041S-MAX and
CY8CPROTO-041TP boards:
- Add ADC node to psoc4100smax.dtsi (SAR v2) and psoc4100tp.dtsi (SAR v3)
- Configure infineon,version property (2 for SMAX, 3 for TP)
- Configure clk-dst for peripheral clock routing
- 041S-MAX: PCLK_PASS0_CLOCK_SAR (0x12)
- 041TP: PCLK_PASS0_CLOCK_SAR (0xc)
- Reference peri_clk_div4 for ADC clock source
- Enable peri_clk_div4 in board common devicetree includes
Signed-off-by: Braeden Lane <Braeden.Lane@infineon.com>
Co-authored-by: Deepika R <deepika@aerlync.com>
Co-authored-by: Sayooj K Karun <sayooj@aerlync.com>
Extend the Infineon peripheral clock control driver to support
ADC peripherals. Adds IFX_RSC_ADC resource type handling and
PSOC4-specific clock destination initialization (set to 0 as
PSOC4 peripherals manage their own clock routing).
Signed-off-by: Braeden Lane <Braeden.Lane@infineon.com>
Co-authored-by: Deepika R <deepika@aerlync.com>
Co-authored-by: Sayooj K Karun <sayooj@aerlync.com>
Add driver for the Infineon SAR ADC peripheral with device tree
binding. The driver uses a generic compatible (infineon,sar-adc)
with an infineon,version property to differentiate IP block
revisions (v2, v3). Features include:
- Single-ended and differential channel configuration
- Configurable resolution (8-12 bits)
- Multiple voltage reference sources (internal, VDDA, VDDA/2, external)
- Channel reference validation against block-level vref-src
- Hardware compensation for SAR v2/v3 single-ended channel limitation
- Interrupt-driven conversion completion
- Integration with peripheral clock control
The driver includes a compile-time per-instance API structure to
correctly report reference voltage to the ADC framework for accurate
raw-to-millivolts conversion.
Tested on CY8CKIT-041S-MAX (SAR v2) and CY8CPROTO-041TP (SAR v3) boards.
Signed-off-by: Braeden Lane <Braeden.Lane@infineon.com>
Co-authored-by: Deepika R <deepika@aerlync.com>
Co-authored-by: Sayooj K Karun <sayooj@aerlync.com>
Removes CONFIG_HARVARD filter from testcase.yaml, adds
RAM tags to nsim/nsim_em, and adds nsim/nsim_em board overlay
so tests are at least built on a Harvard architecture platform
in Zephyr CI.
Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
Adds fixes for build and runtime issues using MWDT:
* Rename sections for llext_memblk.c buffers as MWDT cannot initialize
sys_mem_blocks struct with buffer address when the section name of
sys_mem_blocks struct (its variable name) is identical to the
buffer's section name
* Adds --no-check-sections flag for MWDT on final stages of
linking. Unlike other toolchains, MWDT's default behavior is to
strictly check and fail on section overlap. Using SLIDs requires
overlap; see llext-sections.ld
* Modifies inspect test case's ifdef around rodata sections, as
not all Harvard platforms using MWDT have .rodata_in_data sections -
their creation is triggered by passing the -Hccm flag to CCAC.
As an example, nsim/nsim_em doesn't have them and nsim/nsim_vpx5 does
* Removes -Hccm flag when building with CONFIG_LLEXT_RODATA_NO_RELOC
as it causes CCAC to mark the custom section llext.rodata.noreloc
writable (SHF_WRITE) though it has only read-only data, making it
impossible for for LLEXT to recognize it and put it in the
appropriate region; see llext_load.c's llext_map_sections
* Adds name to unnamed first argument of threads_objects_test_setup,
removing warning about omitting parameter names being a
C2x extension
Also fixes a build warning for GCC about pointer arithmetic in
the INSTR_FETCHABLE macro.
Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
Use DT_GPARENT() so that protection entries are generated for
partitions under the fixed-partitions node, even when an extra
intermediate node is present. This ensures the C40 protection table
is correctly derived from the flash<x> partitions.
Signed-off-by: Petr Buchta <petr.buchta@nxp.com>
Handle the case where the chosen zephyr,flash-controller device has
no flash API (api == NULL). This prevents flash_shell from
dereferencing a NULL api pointer and hard-faulting when no usable
default flash device is available.
Signed-off-by: Petr Buchta <petr.buchta@nxp.com>
Initial generic driver for SPI-NAND devices that expose the ONFI
parameter page. Does not support advanced features such as continuous
reads, software ECC, or optional power down modes.
Configuration comes from devicetree in order to support other modules,
but is validated against the loaded ONFI data at boot.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Due to checksum offloading, the checksum field of a packet must be
zero before sending it to packet to the ethernet controller,
otherwise the computed checksum will be incorrect.
If the packet is bridged, it already has the correct checksum in
place, which will cause the automatically computed checksum to
incorrectly become zero.
In this patch we give bridged packets the special attention they
need.
Signed-off-by: Marcelo Roberto Jimenez <marcelo.jimenez@gmail.com>
Don't run the PSA ITS test on the max32 RV32 targets, since the automatic
erase there ends up erasing the flash region that contains the "host" ARM
application responsible for running the RV32 tests.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
The flash info blocks needed to provide the device ID are not accessible to
the RV32 core on MAX32 devices, so disable this hwinfo driver there.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
Use a custom illegal instruction for the MAX32 RV32 family, since it
doesn't trap on `unimp` or any other write to a read-only/non-existent CSR.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
Enables the sysbuild hello world sample application on MAX32 boards to
demonstrate using the soc's arm cortex-m4 and risc-v cores together. The
build system produces two separate application images, one for each core,
which can be flashed in two steps with the JLink runner.
1. Ensure you can access the serial console configured for the rv32 variant
of your test board, e.g. setting JP4 and JP5 jumpers to connect LPUART
to the USB UART connection CN1 on max32655evkit.
2. Build the sysbuild sample for your board's ARM board ID, which will
automatically build the remote image for the board's RV32 variant, e.g.:
$ west build -p -b max32655evkit//m4 samples/sysbuild/hello_world/ \
-T sample.sysbuild.hello_world
3. Flash both domains at once with the JLink runner:
$ west flash -r jlink
4. Hello world for the RV32 core will be printed to the serial console
Signed-off-by: Maureen Helm <maureen.helm@analog.com>
Add an additional target, max78002evkit/max78002/rv32 for targetting the
secondary RISC-V core on the board.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
The RV32 core does not implement RISC-V mtime, so add a new system
timer driver uses a peripheral timer for this functionality.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
Adds support for the secondary risc-v core on all applicable max32
family socs. The zero-riscy core supports the following instructions:
- RV32I Base Integer Instruction Set
- RV32E Base Integer Instruction Set (optional)
- RV32C Standard Extension for Compressed Instructions
- RV32M Integer Multiplication and Division Instruction Set Extension
(optional)
Includes support for using pinctrl for setting up RV32 debug pin access,
and improved support for launcing the secodary core from the primary ARM
core.
See https://pulp-platform.org/docs/user_manual.pdf
Signed-off-by: Maureen Helm <maureen.helm@analog.com>
Moves some max32 devicetrees from arm to vendor to allow using them on
non-arm targets. This will make it possible to add support for the
secondary risc-v core that exists on these max32 variants.
Signed-off-by: Maureen Helm <maureen.helm@analog.com>
Source tree layout description should use :zephyr_file: since it creates
hyperlinks to GitHub and, more importantly, the references are validated
by the doc build so it guarantees they don't risk going stale.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Clean up the SWD-JTAG port configuration code for STM32F1 series:
- remove check for DT_NODE_HAS_PROP() because there's default in binding
- use a wrapper around DT_ENUM_HAS_VALUE() instead of a bare DT_ENUM_IDX()
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
A special SYS_INIT() callback with hardcoded PRE_KERNEL_1 level 0 priority
inside the STM32 pinctrl driver was configuring the SWD-JTAG ports on
STM32F1 series.
Since this is the only series which requires such configuration, move this
code to the SoC-specific init hook instead (which has almost the same
priority as PRE_KERNEL_1 level 0 - it runs just slightly earlier).
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The CLOCK_CONTROL_NRF_K32SRC_RC_CALIBRATION calibration feature uses
HFCLK (hfxo in devicetree) as reference to calibrate the internal RC.
If the hfxo is not present, calibration is not possible, and if the
driver attempts to do it anyway, HFCLK will be requested wasting
power, and the calibration will never complete.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Avoid dereferencing `stream` in the debug log message when checking
for invalid input parameters.
The previous log printed `stream->ep` and `stream->conn` inside a
combined NULL check, which could trigger static analysis warnings
about a possible NULL pointer dereference.
Align the implementation with the existing pattern used in the file
by logging a generic "Invalid stream" message instead.
No functional change.
Signed-off-by: Gaetan Perrot <gaetan.perrot@spacecubics.com>
- usbd is required by examples to run some samples in
zephyr/samples/subsys/usb
- usb_device is required by examples to run some tests in
zephyr/tests/subsys/usb
Also sort tags list in alphabetical order.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
