In addition to -mslow-flash-data, we must also ensure that the assembler
does not generate literal pools. They are automatically generated by the
LDR pseudo-instruction[1]:
- If the constant can be constructed with a MOV or MVN instruction, the
assembler emits the corresponding instruction.
- Otherwise (when the value does not fit on 16bits), the assembler places
the value in the next literal pool.
No options was found in GNU assembler to disable literal pool generation.
Therefore, this patch explicitly uses MOVT and MOVW when the assembler
would otherwise generate literal pool. Note, that LDR must be kept under
ifdef since Cortex-M0 does not support MOVT/ MOVW.
This patch only change four occurrences of LDR. The other occurrences do
not appear to generate literal pool (likely because the literal values are
< 0xFFFF). If a literal pool is generated in the future, it will introduce
a performance penalty. No other limitations are expected.
[1]: https://developer.arm.com/documentation/dui0204/f/ \
writing-arm-assembly-language/loading-constants-into-registers/ \
loading-with-ldr-rd---const?lang=en
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
On some SoC, no data cache is associated with the main flash. Therefore,
all accesses to data stored in flash, especially literal pools[1] penalizes
performance. Fortunately, GCC and IAR provide options (-mslow-flash-data
and --no_literal_pool) to prevent the generation of literal pools.
Unfortunately, current GCC versions (14.x) do not support -mslow-flash-data
when Thread Local Storage (TLS) variables are used. A patch is currently
under review[2][3] to address this limitation. Without this gcc patch,
using -mslow-flash-data is not very user friendly. The user must rebuild
the libc (CONFIG_PICOLIBC_USE_MODULE=y) without TLS support
(CONFIG_THREAD_LOCAL_STORAGE=n), and must ensure that the application does
not rely on thread-safe "errno".
Because of these interactions with the compiler, this option can't be
automatically selected by the SoC. Thus, this patch leaves the option
hidden. The SoC may expose it if relevant.
[1]: https://en.wikipedia.org/wiki/Literal_pool
[2]: https://gcc.gnu.org/pipermail/gcc-patches/2026-February/707887.html
[3]: https://github.com/zephyrproject-rtos/gcc/pull/65
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Remove MBOX_TI_SECURE_PROXY_PRIORITY in favor of MBOX_INIT_PRIORITY which
by default is set to 40, which is desirable so that the priority dependency
on interrupt controllers like ARM GICv3 gets fulfilled. This change is for
convenience of building at default priorities.
Signed-off-by: Amneesh Singh <amneesh@ti.com>
Change priority from KERNEL_INIT_PRIORITY_OBJECTS to
KERNEL_INIT_PRIORITY_DEFAULT so that the priority dependency on TI secure
proxy mailbox fulfilled.
Signed-off-by: Amneesh Singh <amneesh@ti.com>
Change priority from KERNEL_INIT_PRIORITY_OBJECTS to
KERNEL_INIT_PRIORITY_DEFAULT so that the priority dependency on TISCI
protocol/firmware layer gets fulfilled.
Signed-off-by: Amneesh Singh <amneesh@ti.com>
- Deletes virtual "nxp,cmc-reset-cause" compatible,
as it is covered by existing "nxp,cmc".
- Fixes the issue discovered during discussion in
https://github.com/zephyrproject-rtos/zephyr/issues/104464
#issuecomment-3957779329
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
rtio_cqe_consume() can return NULL, but the result is dereferenced
and released without any NULL check. Add a NULL guard to avoid a
NULL pointer dereference, returning -EIO on failure.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
rtio_cqe_release() is called unconditionally after rtio_cqe_consume(),
but if the consume returns NULL, this passes a NULL pointer to the
release function. Move the release call inside the non-NULL branch.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Implement arch_mem_domain_deinit() for ARM64 to release page tables
back to the pool when a memory domain is de-initialized. This reuses
the existing discard_table() mechanism to recursively free all
sub-tables in the hierarchy.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Increase the Bluetooth RX stack size from the default to 2048 bytes in
the BR/EDR shell test configuration. This provides additional stack
space needed for processing complex Bluetooth Classic operations,
particularly when handling nested SDP attribute parsing.
The increased stack size ensures:
- Sufficient space for recursive SDP attribute parsing
- Prevention of stack overflow during BR/EDR operations
Signed-off-by: Lyle Zhu <lyle.zhu@nxp.com>
Add validation to detect and handle zero-length data elements during
SDP attribute parsing. When the parsed data element length is zero,
log a debug message and return early to avoid unnecessary processing.
This check is placed after parsing the data element length but before
the nesting level validation, ensuring that:
- Empty data elements are gracefully handled without errors
- The parser doesn't attempt to process or skip zero bytes of data
- Subsequent attribute parsing continues normally
This prevents potential issues when SDP records contain empty data
elements and improves parser robustness when handling malformed or
edge-case SDP attribute structures.
Signed-off-by: Lyle Zhu <lyle.zhu@nxp.com>
Move the nesting level check to occur after parsing the data element
length instead of before. This ensures that when the maximum nesting
level is exceeded, the parser can properly skip the nested data by
pulling the correct length from the buffer.
Previously, checking the nesting level before parsing the length meant
the parser would return early without consuming the nested data,
potentially causing parsing errors for subsequent attributes.
The updated logic:
- Parses the data element type and length first
- Checks if maximum nesting level is exceeded
- If exceeded, logs a warning and skips the data element entirely
- Otherwise, proceeds with recursive parsing as normal
This prevents buffer misalignment when deeply nested sequences are
encountered in SDP attribute records.
Signed-off-by: Lyle Zhu <lyle.zhu@nxp.com>
Fix SDP attribute parsing to properly handle nested sequences within
attribute values. Previously, when an attribute value itself contained
a sequence, the parser would not recursively parse the nested sequence,
potentially missing nested attribute data.
Add recursive parsing logic that:
- Detects if the current value buffer contains a sequence type
- Recursively calls sdp_attr_parse() with incremented nest level
- Properly handles nested sequence structures in SDP records
This ensures complete parsing of complex SDP attribute structures that
contain sequences within sequences, such as protocol descriptor lists
or service class ID lists with nested elements.
Signed-off-by: Lyle Zhu <lyle.zhu@nxp.com>
On the stm32U3 with 512K of flash in a single bank,
reset the BKER bit of the FLASH_CR register.
See RefMan Table Flash module organization"
Note "2. When DUALBANK is set to 0 in the option bytes,
for 512-Kbyte single-bank STM32U375/385 devices,
the flash is addressed as a single bank,
and the page numbers are continuous from 0 to 127.
Set BKER = 0 to select bank 1."
Signed-off-by: Francois Ramu <francois.ramu@st.com>
On the stm32U3 series, erase/program operation requires
the voltage range is set to range 1.
This is done before loop on erase/write and the initial voltage
range is restored afterwards.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
On the stm32U3, like it is on the stm32U5 series,
gives the exact nb of pages of 4KB depending on the flash size.
For the page layout, the nb of pages does not depends on the
DUALBANK option byte.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
RAIL depends on the LDMA and TIMER peripherals when Bluetooth Channel
Sounding support has been enabled, so be sure to include those in the
build for such configurations.
Signed-off-by: Johan Hedberg <johan.hedberg@silabs.com>
Removes code duplications and changes uses of Perfetto (viewer) to Trace
Event (format)
Signed-off-by: Maciej Sobkowski <msobkowski@antmicro.com>
Signed-off-by: Krzysztof Sychla <ksychla@antmicro.com>
Signed-off-by: Eryk Szpotanski <eszpotanski@antmicro.com>
Add serial driver support for Renesas RZ/G3E
Signed-off-by: Hoang Nguyen <hoang.nguyen.jx@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
This adds minimal support for board RZ/G3E-SMARC
Signed-off-by: Hoang Nguyen <hoang.nguyen.jx@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Add devicetree to support for Renesas RZ/G3E
Signed-off-by: Hoang Nguyen <hoang.nguyen.jx@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
