This intermediate index page is unnecessary and causes the boards that
are included in its toctree to appear in multiple toctrees, which is a
Sphinx warning.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
This intermediate index page is unnecessary and causes the boards that
are included in its toctree to appear in multiple toctrees, which is a
Sphinx warning.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Update hal_espressif to remove direct ROM linkage
of setjmp and longjmp calls to use the toolchain
implementations instead.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Adds the missing sample.yaml's for building these in CI and with
twister.
Fixes a build issue that came up along the way.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Removed redundant try..except around the code
and fixed a test for that code which was false positive.
Signed-off-by: Łukasz Fundakowski <lukasz.fundakowski@nordicsemi.no>
Memory APS6404L does not support address shift feature.
Since it is being configured for different platforms that uses this
memory, this is cauing an error while building.
Signed-off-by: Missael Maciel <davidmissael.maciel@nxp.com>
Revert a change that broke the stable API function shell_set_bypass.
This reverts commit 6b876dba1ba61b659b1b2d4c3ccd0ac41bd56027.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Revert a change that broke the stable API function shell_set_bypass.
This reverts commit ad7b6aa6ddff677d1590dc2e589e59753862be44.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
fs_open and fs_opendir rely on the structures in the first param
being intialized. (The init functions are documented with the type
declarations.) This simple documentation change mentions this need
to initialize (and emphasizes it). (Users of similar APIs such as
POSIX open and opendir do not expect this initialization need.)
Fixes#97205
Signed-off-by: Paul Hepworth <paulh@vpitech.com>
Correct mdio_stm32_read() and mdio_stm32_write() to return a valid errno
instead of mixing HAL return values and errno return values.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Add missing empty line between local variable definitions and
instructions in eth_stm32_set_mac_config().
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Clean tests on HAL_ETH_SetDMAError() and HAL_ETH_GetDMAError() return
value to explicitly test against 0.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Disabling the internal regulator is immediate so there is no need to check
the state of the Enable bit in the register.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Use the new differential support property instead of relying on the series
name to determine if the ADC supports differential input channels.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Use the new channel preselection property instead of relying on the series
name to determine if the ADC channels need to be preselecting.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Use the new deep powerdown property instead of relying on the series name
to determine if the ADC needs to be be put out or into deep powerdown mode.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Use the new internal regulator property instead of relying on series name
to determine if the regulator should be enabled, and how to check that it
is ready.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
For managing the CCRDY flag, rely on the presence of the LL constant
LL_ADC_FLAG_CCRDY rather than a list of series.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Fill out all ADC nodes of all STM32 with the new properties that apply to
them.
Also moves the status at the end of each node.
Also fixes ADC2 and 3 nodes for STM32F103 and ADC3 node for STM32L471 that
were missing some required properties.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add a bunch of new property for the STM32 ADC in order to simplify the
driver. All these properties are hardware-specific and should not be
modified by users.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add support for SMBus packet error checking (PEC) to the stm32 driver.
This feature allows SMBust communication to be slightly more robust in
the presence of noise, in that packet errors can be detected on the
receive side.
Signed-off-by: Andrew Lewycky <alewycky@tenstorrent.com>
Signed-off-by: Chris Friedt <cfriedt@tenstorrent.com>
Add tests for SMBus packet error correction (PEC). The two primary
utilities tested are
* smbus_pec(): compute the PEC byte for a Block Write
* smbus_read_check_pec(): verify a PEC after
* Read Byte
* Read Word
* Block Read
Signed-off-by: Chris Friedt <cfriedt@tenstorrent.com>
In the case that SMBus hardware does not automatically perform packet
error checking (PEC), provide generic inline functions in
`zephyr/drivers/smbus.h` that can be used by drivers to perform PEC in
software.
Signed-off-by: Chris Friedt <cfriedt@tenstorrent.com>
Signed-off-by: Andrew Lewycky <alewycky@tenstorrent.com>
Move Xuantie supprot from arch/riscv/core/xuantie to the custom common
layer arch/riscv/custom/thead, with the following changes:
1. Rename Kconfig name
CACHE_XTHEADCMO -> RISCV_CUSTOM_CSR_THEAD_CMO
2. Split the original arch/riscv/core/xuantie/Kconfig to
a. arch/riscv/custom/thead/Kconfig: for T-Head extension
b. arch/riscv/custom/thead/Kconfig.core: for T-Head CPU series
(e.g. Xuantie E907)
3. Move cache line size defaults to SoC devicetree
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Update OpenISA RI5CY and Zero-RISCY CSR handling to use RISC-V custom
CSR common code. Move these stuff to 'arch/riscv/custom/openisa':
1. Rename 'soc_ri5cy.h' to 'ri5cy_csr.h' for CSR definitions.
2. Rename 'soc_zero_riscy.h' to 'zero_riscy_csr.h' for CSR definitions.
3. Move CSR context to common macro '__custom_csr_save/restore_context'.
4. Move compiler option '-march=rv32imcxpulpv2' to common code.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
CVA6 supports custom CSR. Move 'cva6.h' to 'arch/riscv/custom/cva6_csr.h',
allowing other SoCs using the CVA6 core to reuse the same CSR definitions.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
GD32VF103 uses Nuclei-specific CSR. Move 'nuclei_csr.h' to
'arch/riscv/custom' to allow reuse across SoCs with the same Nuclei core.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Egis ET171 implements Andes custom CSRs. Enable the following features:
1. Low level initialization of Andes CSRs
2. HWDSP and PowerBrake extensions with context save/restore
3. EXEC.IT extension
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
TLSR951x also supports Andes extended CSR. Reworks the following CSR
handling to use the RISC-V custom CSR common code:
1. Use common macros for HWDSP CSR context save/restore.
2. Use common macros for PFT CSR context save/restore.
3. Use common low-level CSR initialization via __reset hook.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Rework Andes-specific CSR to use RISC-V custom CSR common code.
Move these stuff to 'arch/riscv/custom/andes':
1. Rename 'soc_v5.h' to 'andes_csr.h' for CSR definitions.
2. Replace '_start' with '__reset' hook for low-level CSR initialization.
3. Move CSR context to common macro '__custom_csr_save/restore_context'.
4. Move 'EXECIT' CSR support to common code.
5. Move PMA CSR driver to common code.
6. Use RISC-V common linker.ld instead of SoC-specific linker.ld.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
RISC-V allows custom CSR implementation. Some SoCs from different vendors
may share the same core or the same custom CSR definitions and drivers.
This patch introduces 'arch/riscv/custom', which centralizes support
for custom CSRs, allowing code reuse across SoCs that come from different
vendors. Currently supported thess custom CSR:
1. Andes
2. Nuclei
3. OpenHWGroup CVA6
4. OpenISA RI5CY
5. OpenISA Zero-riscy
6. T-Head Xuantie
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Correct GT911 touchscreen reset line that is connected to GPIO E1,
not E4, on stm32n6570_dk boards. Note that GPIO E4 in connected
to SDcard data bus line D3 on that board.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Fix overriding the test certificates directory for enterprise mode
when using sysbuild. The override already works as expected without
sysbuild.
Signed-off-by: Triveni Danda <triveni.danda@nordicsemi.no>
mbedtls_ssl_get_peer_cid takes size_t, not socklen_t.
c546c1cad1
changed the type of socklen_t to something that is incompatible with native
offloaded sockets, which caused a compiler error.
Signed-off-by: Michael Zimmermann <michael.zimmermann@sevenlab.de>
Neighbor Advertisement (NA) messages without a link-layer address option
are now accepted on point-to-point links. See RFC 7066, ch. 2.2.
Signed-off-by: Jani Hirsimäki <jani.hirsimaki@nordicsemi.no>
Slip is naturally promiscuous, so this patch does nothing but
acknowledge that. Promiscuous mode in slip is important to allow
the interface to be added to a bridge.
Signed-off-by: Marcelo Roberto Jimenez <marcelo.jimenez@gmail.com>
This patch just formats the file before the real patch so that
whitespace changes do not mix with the real code changes.
Signed-off-by: Marcelo Roberto Jimenez <marcelo.jimenez@gmail.com>
Commit 539928d introduced a special behaviour for Microchip QSPI flash
memories into the STM32 QSPI flash driver, to handle the fact that these
memories use the PP_1_1_4 opcode (32H) for the PP_1_4_4 operation
(usually 38H).
The special Microchip-specific behaviour introduced in that commit sets
the address mode for a QSPI 1-1-4 write operation to 4 address lines,
rather than 1 address line, when the write command is configured as
SPI_NOR_CMD_PP_1_1_4. If the write command is configured as
SPI_NOR_CMD_PP_1_4_4, nothing is done and the operation will not succeed.
This behaviour is a bit backwards, as it results in a QSPI flash memory
configured in 1-1-4 write mode using 4 address lines (1-4-4 operation).
It should be the other way round, so that a QSPI flash memory configured
in 1-4-4 mode uses 4 address lines (1-4-4 operation).
This commit changes the Microchip-specific special behaviour to set the
opcode for the specified write mode, rather than using a different write
mode to that which is configured in order to use a valid opcode. This
means that a QSPI flash memory configured in 1-4-4 mode, or without the
writeoc DT property set (defaults to 1-4-4 for quad mode), will operate
in 1-4-4 mode. 1-1-4 mode is unsupported, as before.
Also update the Kconfig option description for
CONFIG_USE_MICROCHIP_QSPI_FLASH_WITH_STM32 to remove references to the
Global Block Protection Unlock instruction - this was added at the same
time as the Microchip-specific special behaviour for the 1-1-4 / 1-4-4
opcode but is distinct from this and is not affected by
CONFIG_USE_MICROCHIP_QSPI_FLASH_WITH_STM32.
Signed-off-by: Ben Marsh <ben.marsh@helvar.com>
Add support for the touch input controller on the STM32H7S78-DK:
- Enable I2C1 on the board
- Add device tree node for the touch controller in the display panel
Signed-off-by: Titouan Christophe <titouan.christophe@mind.be>
Added three functions to support the EAD peripheral:
- Setting and storing key materials for EAD
- Encrypting data for EAD advertisements
- Decrypting data from EAD advertisements
Signed-off-by: Petri Pitkanen <petri.pitkanen@silabs.com>
