Commit graph

136,983 commits

Author SHA1 Message Date
Piotr Kosycarz
23752d2115 tests: drivers: counter: counter_basic_api: fix execution at lm20/ns
Add required overlay.

Signed-off-by: Piotr Kosycarz <piotr.kosycarz@nordicsemi.no>
2025-11-14 15:27:11 +02:00
Piotr Kosycarz
bc8c8f4b3a tests: drivers: i2s: fix execution at lm20/ns
Add required overlay.

Signed-off-by: Piotr Kosycarz <piotr.kosycarz@nordicsemi.no>
2025-11-14 15:27:11 +02:00
Adam Zotow
3804d2f1d1 doc: migration-guide-4.4: Add st,stm32-qspi ssht-enable note
Add migration note for dual-flash configurations requiring ssht-enable
property to reenable sample shifting.

Signed-off-by: Adam Zotow <azo@trackunit.com>
2025-11-14 15:26:31 +02:00
Adam Zotow
40816a81a5 drivers: flash: stm32 qspi: Make delayed data sampling configurable
The QSPI delayed data sampling (SSHIFT) is enabled by default. This
feature is configurable in both XSPI and OSPI drivers. Align with
these drivers and make the feature configurable for QSPI too.

Signed-off-by: Adam Zotow <azo@trackunit.com>
2025-11-14 15:26:31 +02:00
Adam Zotow
54b0c9559c boards: stm32: set ssht-enable property on all qspi dual-flash boards
With ssht-enable property introduced in STM32 QSPI driver the delayed
data sampling (SSHIFT) got disabled for both dual and non-dual flash
configurations. Set ssht-enable property for dual flash boards
to reenable delayed data sampling.

Signed-off-by: Adam Zotow <azo@trackunit.com>
2025-11-14 15:26:31 +02:00
Adam Zotow
e545887d17 dts: bindings: stm32 qspi: add ssht-enable property
This property allows to enable QSPI delayed data sampling (SSHIFT).

Signed-off-by: Adam Zotow <azo@trackunit.com>
2025-11-14 15:26:31 +02:00
Etienne Carriere
b6784734be drivers: gpio: stm32: clean instance init macro indentation
Cleanup indentation in STM32 GPIO controllers device definition
macros. Replace some uses of COND_CODE_1() with IF_ENABLED() that
is bit more explicit.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
2025-11-14 15:26:17 +02:00
Etienne Carriere
8690595a47 drivers: misc: stm32n6_axisram: clean instance init macro indentation
Clean indentation in STM32N6_AXISRAM_INIT() local macro to better
highlight what the macro does. To make it more readable, add a
STM32N6_AXISRAM_MAYBE_INIT() helper macro and use IF_ENABLED()
instead of COND_CODE_0().

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
2025-11-14 15:26:17 +02:00
Etienne Carriere
b3f4439025 drivers: sensor: stm32_digi_temp: clean indentation in init macros
Clean indentation in STM32_DIGI_TEMP_INIT() macro.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
2025-11-14 15:26:17 +02:00
Etienne Carriere
ef51b23a10 drivers: dma: stm32: clean indentation in instance init macros
Clean indentation in macros used to define DMA instances in STM32
DMA drivers.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
2025-11-14 15:26:17 +02:00
Etienne Carriere
fcb9f195a9 drivers: can: stm32: clean indentation in instance init macros
Clean indentation in macros used to define device instances in STM32 CAN
driver.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
2025-11-14 15:26:17 +02:00
Etienne Carriere
97fc64e812 drivers: adc: stm32: clean instance init macro indentation
Cleanup indentation in ADC_STM32_INIT() macro.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
2025-11-14 15:26:17 +02:00
Etienne Carriere
d27e1d6f78 drivers: dac: stm32: clean indentation in instance init macros
Clean indentation in STM32_DAC_INIT() macro.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
2025-11-14 15:26:17 +02:00
Etienne Carriere
b0ccb2295f drivers: stm32: use STM32_CLOCK_INFO_BY_NAME() and friends
Use STM32_CLOCK_INFO(), STM32_DT_INST_CLOCK_INFO(),
STM32_CLOCK_INFO_BY_NAME() and STM32_DT_INST_CLOCK_INFO_BY_NAME()
helper macros in STM32 drivers.

Using these macros ensure the clock division factor is properly
populated according to DT information. Prior these changes some
drivers only got the bus and bits position information and missed
the clock division information which is fine only when this division
factor information is 0.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
2025-11-14 15:26:17 +02:00
Etienne Carriere
c478e7343f include: drivers: clock_control: stm32: add DT clock helper macros
Add helper macros to get clock information from the devicetree:
STM32_DT_INST_CLOCK_INFO_BY_INDEX(), STM32_DT_INST_CLOCK_INFO(),
STM32_CLOCK_INFO_BY_NAME() and STM32_DT_INST_CLOCK_INFO_BY_NAME().

Using these macros or the existing STM32_CLOCK_INFO(), STM32_DT_CLOCKS()
and STM32_DT_INST_CLOCKS() macros ensure clock consumer gets all the
required STM32 clock information that are abstracted by the
STM32 clock drivers resources.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
2025-11-14 15:26:17 +02:00
Etienne Carriere
47717db3be include: drivers: clock_control: stm32: document clock macros
Add a bit of documentation for the existing STM32_CLOCK_INFO()
STM32_DT_CLOCKS().

While at it, fix indentation of STM32_CLOCK_INFO() macro.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
2025-11-14 15:26:17 +02:00
Etienne Carriere
a2ea4f310d include: drivers: clock_control: stm32: remove deprecated macro
Remove STM32_DT_DEV_DOMAIN_CLOCK_SUPPORT macro that is unused and
not planned to be.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
2025-11-14 15:26:17 +02:00
Sebastian Bøe
70f6cf7ea0 soc: nordic: uicr: Move GEN_UICR options into the main Zephyr tree
I initially added the GEN_UICR options to the gen_uicr image's Kconfig
tree only to not pollute the main tree.

But there is a lot of useful help text in the GEN_UICR option's
Kconfig file that I would like users to be able to read/reference from
the docs.

To not increase the complexity of the Kconfig doc generator, we add
the GEN_UICR options to the main tree and have them all be disabled
for builds other than the gen_uicr image.

Being in the main tree has the added benefit of being recognzied by
the compliance checker.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2025-11-14 15:26:06 +02:00
Ruoshan Shi
d185a9aa43 boards: imx93_evk: Document imx-atf TRDC config for M33 DDR access
Add documentation for required imx-atf TRDC configuration changes
to enable M33 core DDR memory access on i.MX93 EVK board.

Signed-off-by: Ruoshan Shi <ruoshan.shi@nxp.com>
2025-11-14 15:25:53 +02:00
Lukasz Fundakowski
03eff37921 twister: Remove unnecessary code
Removed some old code which is not used/needed any more.

Signed-off-by: Lukasz Fundakowski <lukasz.fundakowski@nordicsemi.no>
2025-11-14 15:25:41 +02:00
Lukasz Fundakowski
bd187425f7 twister: Don't print full stack trace in readlines_until method
The readlines_until method is part of the testing framework
(pytest harness) and should not print a full stack trace
when the expected line isn't found. It should also raise
an AssertionError instead of a TwisterHarnessTimeoutException,
allowing users to know that a test failed because the expected
condition did not happen.

Signed-off-by: Lukasz Fundakowski <lukasz.fundakowski@nordicsemi.no>
2025-11-14 15:25:41 +02:00
Fabin V Martin
c84145fe83 boards: sam_e54_xpro: Update pinctrl, DTS, and YAML files
- Update pin control, device tree and board YAML for sam_e54_xpro.

Signed-off-by: Fabin V Martin <Fabinv.Martin@microchip.com>
2025-11-14 15:25:25 +02:00
Fabin V Martin
e4e36f5f28 drivers: i2c: microchip: Add I2C g1 driver
- Add I2C driver for Microchip SERCOM g1.
- Add and update Kconfig files to support the driver.
- Update CMakeLists.txt to include the new driver.

Signed-off-by: Fabin V Martin <Fabinv.Martin@microchip.com>
2025-11-14 15:25:25 +02:00
Fabin V Martin
e8f44b49a2 dts: arm: microchip: sam: Add SERCOM I2C node and binding file.
- Add device tree binding file for Microchip g1 I2C driver

Signed-off-by: Fabin V Martin <Fabinv.Martin@microchip.com>
2025-11-14 15:25:25 +02:00
Camille BAUD
976cd09479 fs: Add a minimal littlefs blocksize
Prevents littlefs from failing when block size is too small to work

Signed-off-by: Camille BAUD <mail@massdriver.space>
2025-11-14 15:25:13 +02:00
Aymen LAOUINI
ba420519af dts: nordic: update nrf9280 nodes in dtsi
- Removed cpurad_uicr and cpuapp_uicr nodes and added uicr node
  at address 0xfff8000 for nRF9280.
- Add bicr node defined in same node as uicr but at offset 800.
- Add tdd_peripherals node.

Signed-off-by: Aymen LAOUINI <aymen.laouini@nordicsemi.no>
2025-11-14 15:25:01 +02:00
Aymen LAOUINI
8f0fbbe8aa boards: nordic: add partitions to memory map for nRF9280
- nRF9280 memory_map_iron is missing periphconf_partition, added this
  partition to mram11 at address 0xe60a000.
- Add secure_storage_partition at 0xe60c000 to memory map. This
  partition is devided in two: cpuapp_crypto_partition and
  cpuapp_its_partition, both are 4KB. Those partitions are used
  by gen_uicr.py script to generate the UICR file.

Signed-off-by: Aymen LAOUINI <aymen.laouini@nordicsemi.no>
2025-11-14 15:25:01 +02:00
Aymen LAOUINI
d9861d77ff soc: nordic: activate uicr generation and use correct dt reg check
- Activate the UICR file generation and PeriphConf for nRF92 application.
- Add condition in reg dt check file to use the correct uicr node name
  for nRF92X.
- Generation of preriphconf entries filters on device names to match
  the first 5 characters to nrf92 or the 6 first characters to nrf54h,
  this information is also used to determine the device SOC_SERIES
  to be either SOC_SERIES_NRF54HX or SOC_SERIES_NRF92X allowing possible
  extension of usage. Still in case of an unknown device of a certain
  family it will use existing configuration while generating
  periphconf entries.

Signed-off-by: Aymen LAOUINI <aymen.laouini@nordicsemi.no>
2025-11-14 15:25:01 +02:00
Krzysztof Chruściński
3c87faea4b tests: drivers: uart: async_dual: Optimize test data handling
Stress test is executed on CPUs with slow clock (16MHz). Handling of test
data in UART_RX_RDY event is optimized to reduce time spent in the
interrupt context. Since payload is always a decrementing sequence, fixed
array is used to compare memory which allows to use standard memcmp
instead of byte by byte comparison.

Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
2025-11-14 15:24:48 +02:00
Krzysztof Chruściński
db9fa069e2 tests: drivers: uart: async_dual: Extend nrf54h20dk configuration
Add workaround timer to instances that are used for reception in the
test.

Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
2025-11-14 15:24:48 +02:00
Krzysztof Chruściński
64b7cabd61 tests: drivers: uart: async_dual: Update configuration for nrf54l
Add timer property to the uart device under test.
Add zephyr,pm-device-runtime-auto to the uart device under test.

Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
2025-11-14 15:24:48 +02:00
Krzysztof Chruściński
c67c3f4359 tests: drivers: uart: async_dual: Extend testing
Extend test with a mode where HWFC is off and receiver is providing
buffers on time. In that case receiver should be able to continuously
receive data without losing any byte (even without HWFC). Additionally,
TX data is chopped to verify that receiver does not loose bytes when
new TX data collides with detected RX timeout.

Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
2025-11-14 15:24:48 +02:00
Krzysztof Chruściński
c5127e677b tests: drivers: uart: async_dual: Add progress report
Add reporting about the test progress. Test lasts few seconds and
progress report helps to see if test stuck or how it is progressing.

Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
2025-11-14 15:24:48 +02:00
Krzysztof Chruściński
f1f0b03aea drivers: serial: nrfx_uarte: Add mode with TIMER byte counting
Add mode to be used on UARTE with frame timeout which is using a bounce
buffers and TIMER to count bytes. This mode shall be used to reliably
receive data without HWFC as frame timeout approach is not 100% reliable
because it can loose or corrupt a byte when new byte arrives after
frame timeout is detected but before it is fully handled. This mode is
similar to the one enabled with CONFIG_UART_x_NRF_HW_ASYNC but
additional bounce buffers are used and UARTE is receiving data to
internal buffers and copies data to the user buffer. Legacy apporach
cannot be used because in new SoC DMA attempts to copy data in words
so when byte is received it stays in the DMA internal buffer until
4 bytes are received or end of transfer happens then internal DMA
buffer is flushed.

Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
2025-11-14 15:24:48 +02:00
Krzysztof Chruściński
9ae8c4edbc drivers: serial: nrfx_uarte: Prepare code for extension
Rearrange code to prepare for upcoming extension that adds special
receive mode.

Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
2025-11-14 15:24:48 +02:00
Krzysztof Chruściński
e20a3acfeb dts: bindings: serial: nrf-uarte: Add timer property
Timer property indicates which TIMER instance should be used for
byte counting. If timer property is present then given instance
is using TIMER to count received bytes.

Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
2025-11-14 15:24:48 +02:00
Jiafei Pan
e2d6af1f55 tracing: rtio: fix building error in rtio header file
This patch is to fix the following building issue:
include/zephyr/rtio/rtio.h:1773:51: error: 'rtio' undeclared
(first use in this function)

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
2025-11-14 11:17:41 +00:00
Michał Stasiak
3ebf29329e soc: nordic: nrf54l: make SoCs select specific symbols
As future nRF54L SoCs may differ in terms of content,
general SOC_NRF54L_CPUAPP_COMMON symbol needs to cover
less symbols. These will be selected by specific SoC based
on support.

Signed-off-by: Michał Stasiak <michal.stasiak@nordicsemi.no>
2025-11-14 12:20:17 +02:00
Thomas Decker
f0749b8301 boards: st: nucleo_h7s3l8 & stm32h7s78_dk: Add runner jlink
Add support for Segger J-Link debug probes connected to MIPI20 connector
on the boards nucleo_h7s3l8 and stm32h7s78_dk.

Signed-off-by: Thomas Decker <decker@jb-lighting.de>
2025-11-14 12:20:05 +02:00
Mathieu Choplain
35a391d47c soc: st: stm32: use series-agnostic STM32 LL headers
Use the series-agnostic STM32 LL headers from the STM32Cube HAL module
instead of series-specific ones in STM32 SoC-specific code. Also remove
inclusion of `stm32XXxx.h` in a few files which already include `soc.h`
who is tasked with doing this inclusion.

Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
2025-11-14 12:19:48 +02:00
Mathieu Choplain
19e1b2b72b samples: boards: st/pm/stop3: use series-agnostic STM32 LL headers
Use the series-agnostic STM32 LL headers from the STM32Cube HAL module
instead of series-specific ones in this sample.

Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
2025-11-14 12:19:48 +02:00
Mathieu Choplain
21b2283fc5 drivers: *: stm32: use series-agnostic STM32 LL headers
Use the series-agnostic STM32 LL headers from the STM32Cube HAL module
instead of series-specific ones in STM32 drivers.

Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
2025-11-14 12:19:48 +02:00
Mathieu Choplain
7fbcd494d8 boards: arduino: *: use series-agnostic STM32 LL headers
Use the series-agnostic STM32 LL headers from the STM32Cube HAL module
instead of series-specific ones in board-specific code of these platforms.

Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
2025-11-14 12:19:48 +02:00
Jun Lin
a922813034 drivers: i2c: npcx: add more timing parameters for I2C clock frequency
I2C Fast-Plus mode (1 MHz) is limited by the source clock.
For example, with a 15 MHz I2C source clock, the max I2C frequency is
~625 kHz. To support higher I2C frequencies, the APBx source clock must
be increased. This commit adds the timing parameters for I2C operation
at higher APBx clocks.

Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
2025-11-14 12:19:29 +02:00
Qingsong Gou
b0662fea5e boards: sifli: sf32lb52_devkit_lcd: enable I2C1
Enable I2C1 device

Signed-off-by: Qingsong Gou <gouqs@hotmail.com>
2025-11-14 12:19:20 +02:00
Qingsong Gou
1b8e3bdaf7 drivers: i2c: add i2c driver for sf32lb platform
Add i2c driver for sf32lb platform

Signed-off-by: Qingsong Gou <gouqs@hotmail.com>
2025-11-14 12:19:20 +02:00
Qingsong Gou
65cdc47bcc dts: arm: sifli: sf32lb52x: define all I2C instances
Add i2c device controller for sf32lb platform

Signed-off-by: Qingsong Gou <gouqs@hotmail.com>
2025-11-14 12:19:20 +02:00
Qingsong Gou
c7b99e9613 dts: bindings: i2c: sf32lb: add sifli,sf32lb-i2c
Add i2c device bindings for sf32lb platform

Signed-off-by: Qingsong Gou <gouqs@hotmail.com>
2025-11-14 12:19:20 +02:00
Qingsong Gou
6b4ced890b drivers: clock_control: sf32lb: add more helper APIs
Add sf32lb_clock_get_status_dt and sf32lb_clock_get_rate_dt

Signed-off-by: Qingsong Gou <gouqs@hotmail.com>
2025-11-14 12:19:20 +02:00
Emil Dahl Juhl
ea68224424 tests: subsys: dsp: utils: include dsp.h
Commit 451afdbaaf9d ("dsp: utils: slim down includes") removed the
inclusion of dsp/dsp.h from dsp/utils.h.
Update the tests to explicitly include dsp/dsp.h.

Signed-off-by: Emil Dahl Juhl <emil@s16s.ai>
2025-11-14 12:19:10 +02:00