Add support for Nucoron NuMaker-M3334KI board
To run the test, check board overlay file for I2C wiring
Signed-off-by: Chun-Chieh Li <ccli8@nuvoton.com>
Complement #99761 that added register includes to too few files.
Fix build error for some boards using these SoCs.
Signed-off-by: Josuah Demangeon <josuah.demangeon@nordicsemi.no>
Minimal changes to OV760 drive to use generic ov767x structures.
- This includes changes to function names.
- Includes changes to defines as necessary.
- Deleted camera_id as no longer required
Signed-off-by: Michael Smorto <CyberMerln@gmail.com>
Add two fixed-regulator nodes to model the load switches on the M5Stack
CoreS3 that control 5V output to the M-Bus/Grove connectors and the USB
VBUS line.
- `bus_out_reg`: controls the BUS_OUT 5V rail (BUS_OUT_EN).
- `usb_otg_reg`: controls USB VBUS output (USB_OTG_EN).
The BUS_OUT regulator is enabled by default to match the behavior of
existing M5Stack boards. USB_OTG remains disabled by default, since
ESP32-S3 does not currently support USB host mode.
Signed-off-by: Chen Xingyu <hi@xingrz.me>
Add a `bus_5v` fixed-regulator node driven by the `BOOST_EN` pin. This
enables drivers and shields to reference the 5V supply through the standard
`vin-supply` property, providing correct power sequencing and runtime
control via Zephyr’s regulator API.
This regulator is equivalent to the `bus_5v` already defined on the M5Stack
Core2 board.
Signed-off-by: Chen Xingyu <hi@xingrz.me>
This commit introduces a new comparison for the ARM (AArch32) architecture
in the GICv3 interrupt controller.
It specifically compares the lower 24 bits of the affinity values,
because there is no aff3 in AArch32 or Arm-v7.
Signed-off-by: Guowei Li <15035660024@163.com>
During the actual development process, it was discovered that the
controller/device' would describe the bus type in the binding. However,
when the two sides did not match, the generated process would not be
affected and there were no any prompts. This made it very difficult for
developers to identify the problem.
I've updated the implementation to:
1. Add a `warn_bus_mismatch` kwarg to `edtlib.EDT()` constructor
(default: False)
2. Add a `--warn-bus-mismatch` flag to gen_edt.py
3. Only show the warning when explicitly opted in
4. Add some checks in the edtlib. When the bus type of the node
does not match the binding requirements, provide some auxiliary
judgment information:
a. bus position of the node
b. available binding types
c. expected binding type.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Allows "egis_et171_spi" to use basic clock information
provided by the clock driver to calculate the runtime
SPI frequency.
Signed-off-by: Jacky Lee <jacky.lee@egistec.com>
The Cadence SPI controller has a hardware issue (Xilinx AR#65885
contains more details) where the RX_NOT_EMPTY (RNE) status bit
reports inconsistent state. This causes the driver to unreliably
detect when RX FIFO contains valid data, leading to transfer
failures and test hangs.
Signed-off-by: Srikanth Boyapally <srikanth.boyapally@amd.com>
Prevents a random occurance whereby sysbuild reconfigures itself
after a reconfiguration for no known discernable reason
Signed-off-by: Jamie McCrae <spam@helper3000.net>
We added Microchip MEC15xx, MEC172x, MEC174x, and MEC175x evalutaion
boards to the GPIO driver gpio_basic_api, gpio_api_1pin, and
gpio_get_direction tests.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Microchip MEC parts have a similar GPIO peripheral block. We
create a unified driver for all parts. NOTE: MEC GPIO interrupt
detection sets active status when changed from interrupt detect
disabled to any enabled mode. Driver ISR and interrupt configuration
implementation includes work-arounds for this issue.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Stores data to output in a temporary buffer and only outputs data
to a file if the data is different to the file's existing data
(assuming it exists). This prevents a random occurance whereby
sysbuild reconfigures itself after a reconfiguration for no known
discernable reason
Signed-off-by: Jamie McCrae <spam@helper3000.net>
The .ARM.extab and .ARM.exidx sections are now mapped under the
zephyr_rodata MMU region, ensuring they remain accessible at runtime.
These sections contain unwind information required for C++ exception
handling, so they must reside in readable memory.
Fixes#96070
Signed-off-by: Simon Maurer <mail@maurer.systems>
This commit fixes build issue when multi level interrupts feature
is enabled, define new macro TEST_1ST_LEVEL_INTERRUPTS_MAX to
support multi level interrupts case.
- error: array subscript 24 is above array bounds of 'volatile
uint32_t[16]' {aka 'volatile unsigned int[16]'}
[-Werror=array-bounds])
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Fix build issue when multi level interrupts is enabled,
define new macro TEST_1ST_LEVEL_INTERRUPTS_MAX to support multi
level interrupts case.
- core_cm33.h:2559:47: error: iteration 496 invokes undefined behavior
[-Werror=aggressive-loop-optimizations]
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Setting a prescaler of 256 would overflow the uint8_t.
Also get cycles calculation was wrong.
Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
Currently, if the role is used like this: :zephyr_file:`blah <link>`
the regex for the link text group is greedy and captures "blah " (note
trailing space). This is incorrect and causes the link to render poorly.
Make regex non-greedy.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Instead of mirroring the ld linker script, the CMake Linker Generator for
ARM was placing the IDT_LIST region right after the Zephyr SRAM. While this
may work fine in most cases, this scheme leads to build errors on some SoCs
such as STM32WBxx, where there are multiple RAM banks that are contiguous
but split over multiple `zephyr,memory-region`s: in such scenarios, the
IDT_LIST region will overlap with one of these `zephyr,memory-region` and
cause a build failure.
Mimic the IDT_LIST placement found in ld linker script to avoid this issue,
except that the region start address is aligned: 0xFFFF8000 instead of
0xFFFF7FFF. This is required by `gen_isr_tables.py` which otherwise errors
out due to finding one more byte than expected in the .intList section.
(The exact reason is not clear, but aligning the region fixes the issue)
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
SOC_MKE16z4 and MKE15z4 (64kB, 48MHz) is now supported by DT
LPFLL clock option with proper frequency select
dts: nxp_ke1xz64.dtsi added.
Tested on board: frdm_ke16z
Signed-off-by: Michael Galda <michael.galda@nxp.com>
Signed-off-by: Hake Huang <hake.huang@nxp.com>
LPFLL (soc: scg: "lpfll_clk") clock source can be now selected
in KE1xz Device tree (nxp_ke1xz.dtsi., board.dts or overlay)
Tested on boards: frdm_ke15z, frdm_ke17z, frdm_ke17z512
Signed-off-by: Michael Galda <michael.galda@nxp.com>
Signed-off-by: Hake Huang <hake.huang@nxp.com>
TSI (Touch Sensing IP) is now supported by DT
for the Kinetis KE1x family
dts: nxp_ke1xz, nxp_ke17z and nxp_ke17z512.dtsi
Tested on freedom boards
Signed-off-by: Michael Galda <michael.galda@nxp.com>
Signed-off-by: Hake Huang <hake.huang@nxp.com>
add driver and dts-binding for kinetis_scg driver
used on ke1xz
Signed-off-by: Hake Huang <hake.huang@nxp.com>
Signed-off-by: Michael Galda <michael.galda@nxp.com>
In install timeout api, the cfg parameter does not make sense to cop, we
can ignore it rather than return an error code to keep forward
compatibility.
Signed-off-by: Yves Wang <zhengjia.wang@nxp.com>
The mcux_adc16 driver's read function fails to validate the user-provided
buffer size when `adc_sequence.options` are used (extra samplings).
The calculation erroneously considered only the size required for one
channel, neglecting the total number of channels in the sequence.
This leads to a **buffer overflow** when reading multiple channels.
Fix this by using `POPCOUNT(sequence->channels)` to determine the
correct channel count and ensure the buffer size is sufficient.
Signed-off-by: Badr Bacem KAABIA <badrbacemkaabia@gmail.com>
The zc143ac72mipi panel can only accept update area
that has even size and coordinates, so the panel
driver was updated to maintain a buffer to collect
all dirty areas. This buffer shall have address and
pitch alignments which compliant to the board's display
driver's requirement, and can be placed outside of ram.
Update the board specific overlay to add such configurations.
Signed-off-by: Kate Wang <yumeng.wang@nxp.com>
1. Fix wrong backlight pin in driver overlay
2. Remove the power-on pin configuration in code and binding, and
add mipi display panel regulator in panel overlay instead. Set
regulator-boot-on' to true means the power-on pin will be enabled
uring system boot.
3. Remove 'last_known_framebuffer' from panel data structure. It is
not used anywhere
4. Fix bug in 'co5300_set_pixel_format' function.
5. Fix the issue that the panel does not support start coordinates
and the width/height of the updated area being odd value.
Solution: In panel driver, maintain a full screen-sized buffer,
its address and pitch alignment is configurable in device tree
and shall be compliant with the display controller's requirements.
It can be placed in RAM or if the RAM space is not enough it can
also be placed in other memory resion. When there is a frame
update request, the updated area will be first filled to the
buffer, if the area's size or coordinate is odd, adjust the value
so the real updated area covers the requested updated area, then
use this buffer to send pixel to panel, this can ensure the
updated area's size and coordinate are always even.
Signed-off-by: Kate Wang <yumeng.wang@nxp.com>
The mimxrt700_evk uses DC8000 to drive panel which requires a 64
byte align of buffer address and stride.
Signed-off-by: Kate Wang <yumeng.wang@nxp.com>
If the stack is in ITCM, DTCM, or FlexRAM OCRAM, flexram_dt_partition()
may change its contents. The comment on flexram_dt_partition()
acknowledges that, stating that it's inlined because it "cannot use
[the] stack". But we currently call SystemInit(), which is not inlined
and does use the stack, prior to flexram_dt_partition()! Fix that issue
by reordering the calls.
It seems to me that flexram_dt_partition() would be safer as a
soc_early_reset_hook implemented in assembly, but this fix does work for
the moment. Tested on an i.MX RT1061, with the stack in FlexRAM OCRAM
and entering Zephyr with all FlexRAM allocated to ITCM and DTCM.
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
If the stack is in ITCM, DTCM, or FlexRAM OCRAM, flexram_dt_partition()
may change its contents. The comment on flexram_dt_partition()
acknowledges that, stating that it's inlined because it "cannot use
[the] stack". But we currently call SystemInit(), which is not inlined
and does use the stack, prior to flexram_dt_partition()! Fix that issue
by reordering the calls.
It seems to me that flexram_dt_partition() would be safer as a
soc_early_reset_hook implemented in assembly, but this fix does work for
the moment. Tested on an i.MX RT1061, with the stack in FlexRAM OCRAM
and entering Zephyr with all FlexRAM allocated to ITCM and DTCM.
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
The irq_lock area including net_pkt_rx_alloc_with_buffer() was causing
error "Context switching while holding lock!".
Actually we didn't have any hardware access to protect in netc_eth_rx,
so just removed irq_lock.
Fixes#99694
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
