The QDEC driver does not use any of the functions implemented in the TIM
LL full driver module (`stm32XXxx_ll_tim.c`), only those provided by the
LL header (`stm32XXxx_ll_tim.h`).
Disable compilation of the unnecessary full driver module.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The RTC driver does not use any of the functions implemented in the LL full
driver module (`stm32XXxx_ll_rtc.c`), only those provided by the LL header
(`stm32XXxx_ll_rtc.h`).
Disable compilation of the unnecessary full driver module.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
STM32H5 series now uses the dedicated `flash_stm32_xspi` driver instead.
Remove all quirks related to H5 in the STM32 OSPI driver.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
When CONFIG_NO_OPTIMIZATIONS=n then kobject area can get inflated.
Some targets are currently fail to compile due to that.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
When the number of input bits changes, the value in the `CR_DATASIZE`
register should be modified accordingly.
The CRC32_C algorithm does not require the result to be XOR
Signed-off-by: Haoran Jiang <halfsweet@halfsweet.cn>
The buffer length check was not updated with the change to the H4 header
push location (changed in 6113230c). As the complete buffer is now
provided, a buffer of length `SPI_MAX_MSG_LEN` is now valid.
Signed-off-by: Jordan Yates <jordan@embeint.com>
No activity from this user for over 2 years. It is likely that they're
now @ppryga-nordic but since it doesn't seem anybody noticed the
discrepancy in many years, I think it is safe to drop the entry :)
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Update the memory layout to use the SRAM3 node for board RZ/V2H core CR8
Signed-off-by: Phuc Pham <phuc.pham.xr@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
- Enable the DTCM region in soc.c
- Apply MPU configuration for the new memory region (itcm, dtcm,
sram,...)
- Turn on the Kconfig to relocate the vector table to 0x0.
Signed-off-by: Phuc Pham <phuc.pham.xr@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Zephyr generates the system call headers using CMake custom
targets and various scripts. Some platforms, like the Nordic onces,
reuse some files located in Zephyr inside the TF-M build as well.
Because of this the generated Zephyr headers needs to exist before
TF-M starts the build process in order to succeed.
This adds a dependency to make sure TF-M starts building after the
Zephyr custom command which generates the system call headers is
executed.
Signed-off-by: Georgios Vasilakis <georgios.vasilakis@nordicsemi.no>
This patch allows a DMA device that is part of a power domain to start
the test in a suspended power-management state. If another device makes
the power domain active (for example, the console UART), the DMA device
within the same power domain may enter a suspended state.
The test will now verify that the device is suspended/off before the
test begins, active during the test, and restored to its initial state
at the end.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
During L2 page table duplication, there are cases where we
should copy the table over instead of restoring the PTEs.
Add the ability to copy the table over.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds a spinlock to guard page table counter updates.
For some reasons, without this, xt-clang generated code would
result in incorrect counter update possibly due to memory
access ordering (though GCC generated code works fine without
the spin lock).
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Use CONFIG_CACHE_HAS_MIRRORED_MEMORY_REGIONS instead.
The new kconfig reflects more correctly on what is going on
in hardware. Also, this is not enabled by default if CPU
cache is not coherent. CPU cache can be incoherent and yet
there are no mirrored memory regions. Those relying on this
deprecated default behavior has their config adding
CONFIG_CACHE_HAS_MIRRORED_MEMORY_REGIONS separately.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This removes the following kconfigs:
() CONFIG_XTENSA_RPO_CACHE
() CONFIG_XTENSA_CACHED_REGION
() CONFIG_XTENSA_UNCACHED_REGION
The associated feature is actually SoC specific and not general
architecture feature. Since the only user of these have its own
implementation, we can now safely remove these.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This re-implements the CONFIG_XTENSA_RPO_CACHE and its cached
and uncached region support in the SoC layer. This is in
preparation for removing RPO cache in the architecture layer
as this is a SoC feature and not an architecture feature.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Make sure code using these kconfigs are only compiled if they
are defined. They will be removed later. But for now, we need
these #ifdef to avoid breaking the build when we move these
caching functions to SoC layer.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This allows SoC to define their custom cache related functions
and are used by sys_cache_*() functions.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
arch_mem_coherent() is cache related so it is better to move it
under cache subsys. It is renamed to sys_cache_is_mem_coherent()
to reflect this change.
The only user of arch_mem_coherent() is Xtensa. However, it is
not an architecture feature. That's why it is moved to the cache
subsys.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The macro ARCH_XTENSA_SET_RPO_TLB is only used for Intel Audio
DSP. The specific memory mapping requiring this is SoC specific
feature and not a feature on Xtensa in general. It should not be
declared in the architecture layer. So move it.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds a kconfig to indicate a memory mapping where physical
memory regions are both mirrored and mapped in different
addresses. Accessing one set of addresses is via CPU cache
while the other is directed to memory.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This moves the ace-link.ld into include/linker to indicate it is
to be included by the main linker script. Also rename it to
ace-link-mirrored.ld to indicate that it is for the mirrored
cache configuration.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The Zephyr linker script usually puts something before
z_mapped_start (where .text is), for example, vecbase vectors.
So we need to reserve those space or else k_mem_map() would be
mapping those which may result in faults.
To avoid mapping there, CONFIG_ARCH_HAS_RESERVED_PAGE_FRAMES
needs to be used. Since it is common when MMU is enabled, we
should enable it by default using imply. All current Xtensa
MMU SoCs all have this selected anyway. Using 'imply' instead
of 'select' is to allow it to be disabled if so desired.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This removes CONFIG_XTENSA_MMU_DOUBLE_MAP and its associated
code. The double mapping of a page into both cached and
uncached memory regions should be done in SoC and application,
as it gives finer control on what actually is being mapped.
For example, if a page only needs to mapped in cached region,
there is no need to map it in the uncached region. This may
save the need to allocate a L2 page table for it, and saves
some memory.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Rework the SoC MMU mappings in preparation for removal of
double mapping code in Xtensa architecture code. This will let
the SoC layer and application to fine tune memory mappings
instead of having double mapping forcibly applied everywhere.
The modified mapping array mimics what the double mapping
would have done simply to have the same behavior. Future
optimizations can be done to remove unnecessary mappings.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds the arch default MMU mappings into the SoC mapping
array. This is in preparation of not forcibly doing double
mapping in architecture code as this type of double mapping
should be specified for individual regions. This allows
the SoC layer to fine tune the mappings as not anything
needs to be double-mapped.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Adds kconfig CONFIG_XTENSA_MMU_USE_DEFAULT_MAPPINGS for arch
code to initialize the page tables with a few default mappings
covering text, data, BSS and RODATA. Disabling this allows
the SoC to customize and fine-tune the mappings if needed.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Moves the HiFi related kconfigs to their respective SoC
kconfigs as it is specific to the SoC... and this requires
creating new kconfigs for each SoC series.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The newlib that comes with the Xtensa toolchain is very old,
and is not thread-safe _at all_. So the newlib tests would
fail sometimes but pass in the next run. So skip the newlib
tests for intel_adsp platforms.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
