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136,983 commits

Author SHA1 Message Date
Jérôme Pouiller
6966bbca19 modules: wiseconnect: SL_CODE_CLASSIFY() is disabled
Normally, SL_CODE_CLASSIFY() renames the symbols. SL_CODE_COMPONENT_* is
here to provide the prefix the user want to use for a specific component.

However, since SLI_CODE_CLASSIFICATION_DISABLE is set, SL_CODE_CLASSIFY()
is a no-op and SL_CODE_COMPONENT_* are useless.

Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
2026-01-26 14:16:31 +01:00
Jérôme Pouiller
7c03a18362 modules: wiseconnect: Make all public headers available
Include directives in hal_silabs only specify the header filename without
specifying any subdirectory. They rely to a bunch -I directives to find
the correct paths.

In addition, the hal_silabs sources tends to include header from the other
subdirectory in an anarchic way. These header are generally only required
to compile functions that are finally unused by Zephyr drivers.

There has been some tentative to conditionally include the external
headers. However, it broke the code compilation and prevent the use of
IS_ENABLE() (so #define has to be widely used leading to real mess). It is
cleaner to just add all the included paths to the compiler command line.

A few private headers path are still declared per components.

Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
2026-01-26 14:16:31 +01:00
Jérôme Pouiller
8cb47252ba modules: wiseconnect: Avoid globbing in zephyr_code_relocate()
To avoid any confusion, we prefer to explicitly reference the compiled
files.

Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
2026-01-26 14:16:31 +01:00
Jérôme Pouiller
6d5c230f50 modules: wiseconnect: Drop useless files
Since commit edbd4186  ("wiseconnect: Patch for sli_si91x_clock_manager.c")
in hal_silabs repository, a few files became useless.

Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
2026-01-26 14:16:31 +01:00
Jérôme Pouiller
2dcaab2942 modules: wiseconnect: Simplify the names
`_DIR' suffix is superfluous in the CMakeLists.txt. In addition, COMMON_DIR
is rarely used and not descriptive enough.

Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
2026-01-26 14:16:31 +01:00
Jérôme Pouiller
7bf5f68336 modules: wiseconnect: Fix indentation
Don't pollute following-up commits with cosmetics changes.

Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
2026-01-26 14:16:31 +01:00
Jérôme Pouiller
1de7b1ced7 drivers: clock_control: siwx91x: Clean up siwx91x_clock_set_rate()
Simplify siwx91x_clock_set_rate() a bit.

Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
2026-01-26 14:16:31 +01:00
Jérôme Pouiller
e6302b1b74 drivers: rng: siwx91x: Avoid direct access to the clock
Currently, silabs,siwx91x-rng directly write clock hardware block. Change
that to properly rely on clock driver.

Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
2026-01-26 14:16:31 +01:00
Jérôme Pouiller
d908778a21 drivers: rng: siwx91x: Fix naming
Align naming rules with the other drivers.

Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
2026-01-26 14:16:31 +01:00
Jérôme Pouiller
a2ca0280ed drivers: adc: siwx91x: Fix SIWX91X_CLK_ADC
RSI_ADC_PowerControl() enables the clock AND power on the ADC hardware
block.

The clock control should only access to the clock hardware block.

Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
2026-01-26 14:16:31 +01:00
Jérôme Pouiller
a78cd3464e drivers: adc: siwx91x: Fix use of RSI_ADC_ClkDivfactor()
RSI_ADC_ClkDivfactor() is called from system clock_control. But in fact, it
controls the internal division factor of the ADC hardware block.

Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
2026-01-26 14:16:31 +01:00
Jérôme Pouiller
e2f4fc15af drivers: adc: siwx91x: Fix use of ADC_CONTEXT_USES_KERNEL_TIMER
ADC_CONTEXT_USES_KERNEL_TIMER is required for ADC_CONTEXT_INIT_TIMER().
However, it should be defined in the Zephry driver, not in the Wiseconnect
integration.

Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
2026-01-26 14:16:31 +01:00
Afonso Oliveira
ca062130c9 arch: riscv: call IMSIC secondary init on SMP boot
Invoke IMSIC secondary initialization during RISC-V SMP bring-up.

Signed-off-by: Afonso Oliveira <afonsoo@synopsys.com>
2026-01-26 14:16:22 +01:00
Afonso Oliveira
c11baf0942 drivers: interrupt_controller: riscv: imsic: add SMP init helper
Add per-hart IMSIC initialization helper for secondary CPUs in SMP builds.

Signed-off-by: Afonso Oliveira <afonsoo@synopsys.com>
2026-01-26 14:16:22 +01:00
Afonso Oliveira
833edaf7c8 drivers: interrupt_controller: riscv: add IMSIC driver
Add IMSIC driver implementation with atomic mtopei claim using csr_swap
and EIE configuration for interrupt enable/disable.

Signed-off-by: Afonso Oliveira <afonsoo@synopsys.com>
2026-01-26 14:16:22 +01:00
Afonso Oliveira
cdbf3b787e arch: riscv: add csr_swap macro for atomic CSR read-write
Add csr_swap() macro that performs an atomic CSR read and write using
the csrrw instruction. This completes the set of CSR access primitives
alongside the existing csr_read, csr_write, csr_read_set, and
csr_read_clear macros.

The csrrw instruction atomically reads the current CSR value into a
register while simultaneously writing a new value, which is required
for operations like IMSIC interrupt claiming where the read and write
must be indivisible.

Signed-off-by: Afonso Oliveira <afonsoo@synopsys.com>
2026-01-26 14:16:22 +01:00
Afonso Oliveira
742685afbd include: drivers: interrupt_controller: riscv: add IMSIC header
Add public IMSIC driver API header (claim and EIID control).

Signed-off-by: Afonso Oliveira <afonsoo@synopsys.com>
2026-01-26 14:16:22 +01:00
Afonso Oliveira
39b0d2b0b6 dts: bindings: riscv: add IMSIC binding
Add devicetree binding for the RISC-V IMSIC (Incoming Message-Signaled
Interrupt Controller).

Signed-off-by: Afonso Oliveira <afonsoo@synopsys.com>
2026-01-26 14:16:22 +01:00
Lyle Zhu
53ada3ba72 tests: Bluetooth: Support unpair for classic bonding
The bonding information of classic can be deleted by calling the
function `bt_br_unpair()`.

The BTP command `unpair` does not support the case. Calling the
function `bt_br_unpair()` to delete classic bonding information if
the address is BR type when the BTP command `unpair` is received.

Signed-off-by: Lyle Zhu <lyle.zhu@nxp.com>
2026-01-26 14:15:29 +01:00
Fin Maaß
8cc8239efa riscv: require riscv,isa-base and riscv,isa-extensions
require `riscv,isa-base` and `riscv,isa-extensions` dt props
to be set.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2026-01-26 14:15:18 +01:00
Fin Maaß
06027c74fd docs: migration-guide: mention riscv changes
mention riscv changes.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2026-01-26 14:15:18 +01:00
Fin Maaß
204029f12c riscv: deprecate riscv,isa dt prop
deprecate riscv,isa dt prop

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2026-01-26 14:15:18 +01:00
Fin Maaß
2cea7b0582 thead: riscv: use riscv,isa-extensions dt prop
use riscv,isa-extensions dt prop for riscv cpus.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2026-01-26 14:15:18 +01:00
Fin Maaß
869845d6ab aesc: riscv: use riscv,isa-extensions dt prop
use riscv,isa-extensions dt prop for riscv cpus.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2026-01-26 14:15:18 +01:00
Fin Maaß
ed6a969849 andestech: riscv: use riscv,isa-extensions dt prop
use riscv,isa-extensions dt prop for riscv cpus.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2026-01-26 14:15:18 +01:00
Fin Maaß
01bc8b2351 egis: riscv: use riscv,isa-extensions dt prop
use riscv,isa-extensions dt prop for riscv cpus.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2026-01-26 14:15:18 +01:00
Fin Maaß
8f69f66059 gd: riscv: use riscv,isa-extensions dt prop
use riscv,isa-extensions dt prop for riscv cpus.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2026-01-26 14:15:18 +01:00
Fin Maaß
fb1aeeb346 intel: niosv: riscv: use riscv,isa-extensions dt prop
use riscv,isa-extensions dt prop for riscv cpus.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2026-01-26 14:15:18 +01:00
Fin Maaß
5b0a847098 ite: riscv: use riscv,isa-extensions dt prop
use riscv,isa-extensions dt prop for riscv cpus.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2026-01-26 14:15:18 +01:00
Fin Maaß
74e5e8fc13 lowriscv: riscv: use riscv,isa-extensions dt prop
use riscv,isa-extensions dt prop for riscv cpus.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2026-01-26 14:15:18 +01:00
Fin Maaß
1773d0538d microchip: riscv: use riscv,isa-extensions dt prop
use riscv,isa-extensions dt prop for riscv cpus.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2026-01-26 14:15:18 +01:00
Fin Maaß
e9333dbe24 neorv32: riscv: use riscv,isa-extensions dt prop
use riscv,isa-extensions dt prop for riscv cpus.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2026-01-26 14:15:18 +01:00
Fin Maaß
bbb216584e openhwgroup: riscv: use riscv,isa-extensions dt prop
use riscv,isa-extensions dt prop for riscv cpus.

also combines both SOC_CV64A6 variants

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2026-01-26 14:15:18 +01:00
Fin Maaß
6733437c95 openisa: riscv: use riscv,isa-extensions dt prop
use riscv,isa-extensions dt prop for riscv cpus.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2026-01-26 14:15:18 +01:00
Fin Maaß
9b570e90f2 raspberrypi: riscv: use riscv,isa-extensions dt prop
use riscv,isa-extensions dt prop for
raspberrypi riscv cpus.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2026-01-26 14:15:18 +01:00
Fin Maaß
1c72c78d5f sensry: riscv: use riscv,isa-extensions dt prop
use riscv,isa-extensions dt prop for
sensry riscv cpus.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2026-01-26 14:15:18 +01:00
Fin Maaß
30ff2d3cae bflb: riscv: use riscv,isa-extensions dt prop
use riscv,isa-extensions dt prop for
bflb riscv cpus.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2026-01-26 14:15:18 +01:00
Fin Maaß
783ebd98bc sifive: riscv: use riscv,isa-extensions dt prop
use riscv,isa-extensions dt prop for
sifive riscv cpus.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2026-01-26 14:15:18 +01:00
Fin Maaß
617a903946 snps: riscv: use riscv,isa-extensions dt prop
use riscv,isa-extensions dt prop for
snps riscv cpus.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2026-01-26 14:15:18 +01:00
Fin Maaß
be7285c086 starfive: riscv: use riscv,isa-extensions dt prop
use riscv,isa-extensions dt prop for
starfive riscv cpus.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2026-01-26 14:15:18 +01:00
Fin Maaß
72bd920bfa telink: riscv: use riscv,isa-extensions dt prop
use riscv,isa-extensions dt prop for
telink riscv cpus.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2026-01-26 14:15:18 +01:00
Fin Maaß
95ff5d4247 wch: riscv: use riscv,isa-extensions dt prop
use riscv,isa-extensions dt prop for
wch riscv cpus.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2026-01-26 14:15:18 +01:00
Fin Maaß
a44b46887f espressif: riscv: use riscv,isa-extensions dt prop
use riscv,isa-extensions dt prop for
espressif riscv cpus.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2026-01-26 14:15:18 +01:00
Fin Maaß
1ab82c808c nordic: riscv: use riscv,isa-extensions dt prop
use riscv,isa-extensions dt prop for
nordic riscv cpus.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2026-01-26 14:15:18 +01:00
Fin Maaß
33e5ee9c31 renode: riscv: use riscv,isa-extensions dt prop
use riscv,isa-extensions dt prop for
renode riscv boards.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2026-01-26 14:15:18 +01:00
Fin Maaß
cf921b08d4 efinix: riscv: use riscv,isa-extensions dt prop
use riscv,isa-extensions dt prop for
efinix riscv boards.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2026-01-26 14:15:18 +01:00
Fin Maaß
d20d43b63d qemu: riscv: use riscv,isa-extensions dt prop
use riscv,isa-extensions dt prop for
qemu riscv boards.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2026-01-26 14:15:18 +01:00
Fin Maaß
673994458b litex: use riscv,isa-extensions dt prop
use riscv,isa-extensions dt prop for
litex vexriscv soc.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2026-01-26 14:15:18 +01:00
Fin Maaß
974d752293 riscv: make riscv,isa dt prop no longer required
make riscv,isa dt prop no longer required,
as it is is not really used by anyrhing in zephyr
and we now have a alternative (riscv,isa-base
and riscv,isa-extensions).

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2026-01-26 14:15:18 +01:00
Fin Maaß
e2fd8e6de7 riscv: use riscv,isa-extensions dt prop
implement and use riscv,isa-extensions
dt prop, like in linux
https://www.kernel.org/doc/Documentation/devicetree/bindings/riscv/extensions.yaml
to set the riscv extentions.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2026-01-26 14:15:18 +01:00