LUT sizes directly reflects the global data when enabled in dts
(even if no or few pins are really consumed). Also the PINCM
numbering across the series (g, l and c) is within 255, so fix
to use uint8_t to save the global space.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
All the HAL API/wrapper depends on PINCM indexing, which cannot
be derived from neither pin number nor the address offset.
With current approach, update the LUT table of possible PINCM's
for L series with GPIO A, B and C banks.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
mspm0 family of SoC series is split into three category,
mspm0g - high performance
mspm0l - low power
mspm0c - entry level
With G already part added, add support for L series of SoC's.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
although udiv is represented in clock tree of L series, this is
not really present or controllable from SYSCTL registers. Enable
udiv only if present in dts.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
mspm0 series (currently g, l and c) shares the common SoC
level init functions and pin control/muxing configurations.
To avoid duplication for each series, create a common path
and move the SoC and pin control definitions.
Other common functionalities like Power Management, Power off
handling will be added in future, which will be common across
series.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
MSPM0Lx series supports pin function upto 11 i.e 0xb, extend
the pin control function number to 11.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
Flash size and address is extracted from dts, which will be common
for all the upcoming series of SoC's like MSPM0L, MSPM0C. Move the
flash address and size to soc level defconfig.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
Update manifest to point MSPM0L series support.
Currently it only supports L2228's devicetree pin functions.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
Add overlays used for testing differential mode support in STM32 ADC
driver:
- Nucleo F303K8
- Nucleo H753ZI
Signed-off-by: Matt Rodgers <mrodgers@witekio.com>
Differential mode support consists of:
- If differential mode is supported by the underlying hardware AND at
least one differential channel is enabled in the devicetree for this
ADC instance, then perform a differential mode calibration in addition
to the usual single ended calibration during initialisation.
- Set channels to the appropriate differential or single ended mode
during channel setup.
Currently the N6 series is not supported even though the underlying
hardware supports differential mode, due to complications in the
calibration procedure.
Signed-off-by: Matt Rodgers <mrodgers@witekio.com>
Co-authored-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
TI MSPM0 timer module has capture block used to capture timings of input
signal. Add a support for TI MSPM0 PWM capture.
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
Add test case to cover RAM vector table relocation when
CONFIG_SRAM_VECTOR_TABLE is selected
Signed-off-by: Ioannis Damigos <ioannis.damigos.uj@renesas.com>
Use --test-pattern to filter scenarios using regular expressions, for
example:
./scripts/twister --test-pattern '^kernel.semaphore.*' -v
will run all those test using this identifier pattern, and nothing else.
Multiple patterns are possible.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Certain implementations require more stack to operate.
Increase the stack size to avoid overflows.
Signed-off-by: Tomi Fontanilles <tomi.fontanilles@nordicsemi.no>
A clone of the zms test, using the retention backend, with support
for nrf52840dk and qemu_cortex_m3
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Now when role is sink and source sends data, stream recv callback is
not registered, apps works fail. so stream recv callback should be
checked.
Signed-off-by: Cheng Chang <cheng.chang@nxp.com>
Configure the initial pin state of the SPIM peripheral to SLEEP, not
DEFAULT. This fixes the pins being configured in DEFAULT until the first
time the interface is used if `zephyr,pm-device-runtime-auto` is
enabled.
Signed-off-by: Jordan Yates <jordan@embeint.com>
A kernel panic was observed on a platform when k_sem_give() was called
in npcx_kbd_ksi_isr(). From the panic information, it appears that
the semaphore was used before it was initialized. This commit prevents
the potential issue by enabling the interrupt only after
the input_kbd_matrix_common_init() function is called
(where the semaphore is initialized).
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Configure the initial pin state of the UARTE peripheral to SLEEP, not
left uninitialised. This fixes the pin configuration not being set until
the interface is used if `zephyr,pm-device-runtime-auto` is enabled.
Signed-off-by: Jordan Yates <jordan@embeint.com>
If a compliance test itself throws an exception, the entire script is
aborted.
Update this by capturing the exception and failing only the test itself.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Initialize 'dl_file' to 'None' before the logic that determines
which binary file to load.
Resolves the E0606 Pylint warning.
Signed-off-by: Georgij Černyšiov <geo.cgv@gmail.com>
clang reports a warning about a label followed by a variable
declaration:
label followed by a declaration is a C23 extension
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
Fix one leftover unaligned access warning generated by clang:
warning: taking address of packed member 'th_seq' of class or
structure 'tcphdr' may result in an unaligned pointer value
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
RP2350 provides a function to get OTP-backed chip ID. Prefer using this
on supported platforms for these reasons:
- a secure internal identifier, same as read by picotool
- works on flashless boards
- does not conflict with code running in XIP mode (e.g. when the other
core tries to access device ID)
- when used with USB HWID serial number will match one BootROM has
Signed-off-by: Dmitrii Sharshakov <d3dx12.xx@gmail.com>
Co-authored-by: Alexander Wachter <alexander@wachter.cloud>
Supports the EVL/Xenomai4 benchmarking tool as described in the
documentation. The benchmarking tool is accessed via the latmon service.
This code uses the J2 socket on FRDMk64-F:
PIN_20: tx pulse to SUT
PIN_18: rx ack from SUT
The client code running on the SUT shall monitor the falling edge of
PIN_20.
Example usage from the latmus client running Xenomai4:
$ latmus -I gpiochip2,23,falling-edge \
-O gpiochip2,21 -g"histogram" \
-z broadcast
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Updates the Xtensa hardware documentation to provide details about
the new lazy HiFi sharing model.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
When lazy HiFi context switching is enabled, the system starts with
the HiFi coprocessor disabled. Should the thread use that coprocessor,
it will generate an exception which in turn will enable the coprocessor
and save/restore the HiFi registers as appropriate. When switching
to a new thread, the HiFi coprocessor is again disabled.
For simplicity, there are no restrictions as to which thread is allowed
to use the coprocessor.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
The intent of arch_coprocessors_disable() is to replace
arch_float_disable() in halt_thread() for the FPU will not
always be the only coprocessor that will need to be disabled.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
Adds a customized _cpu_arch structure for Xtensa so that it contains
a pointer to the thread that 'owns' the hifi register set for use
with lazy save/restore.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
As the BSA can not be used when lazy HiFi context switching is
used, a more permanent and predictable location in which to store
the registers is required. To this end ...
1. reserve some space in the arch-specific portion of the k_thread
structure for those registers.
2. clear that region when the thread is created.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
Splits HiFi sharing into two different models.
1. XTENSA_EAGER_HIFI_SHARING - unconditional save/restore
of the HiFi registers when context switching
2. XTENSA_LAZY_HIFI_SHARING - on demand save/restore of
of the HiFi registers. If a thread does not use the
HiFi registers, they are neither saved nor restored.
To maintain backwards compatibility, the eager model is the
default model when XTENSA_HIFI_SHARING is enabled.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
- In bap_unicast_client, it was assumed that ASE is binded with CIS
handler during sending "received_stop_ready" to unicast_server.
- In case where unicast_client has not started the stream with
"receiver_start_ready" att command to server, but wants to disable
ASE which was Enabled previously (but not stream!) causes failure
since there is no cis_create has happened and linked to ASE.
- In BAP_TS, "BAP/UCL/SCC/BV-103-C" has a same test conditions where
client first enables the ASE, disable the ASE, and expecting
"receiver_stop_ready" att command from client to server followed by
server notification to enter its ASE in QoS_configured state.
- Removed this condition checks to send expected att command to
server from Enabling ASE state to Disable ASE.
Signed-off-by: Nirav Agrawal <nirav.agrawal@nxp.com>
Systick is already enabled before late hook got called. In certain
circumstances systick could flooding the core and thus only handling
systicks. Enabling cache earlier using soc_early_init_hook ensures
that systick get handled quicker.
Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
Make this option default and reduce amount of details displayed by
twister.
This options has been enabled in CI for a while now with the intention
of making it default.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Previously, the CMSDK APB dual timer driver hardcoded the counter
clock frequency to 24 MHz, which limits reuse across SoCs and
boards with different timer clock sources.
This patch replaces the hardcoded frequency with a value derived
from the device tree's `clocks` phandle, using the
`clock-frequency` property of the referenced clock controller node.
If the property is missing, it falls back to a default 24 MHz.
Signed-off-by: Lidor T <lidor@exibit-iot.com>
