Fix clock config logic of wm8962 and wm8904 drivers, so that both can be
properly configured for master (generating BCK and WS) and slave
(receiving those) operation.
Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
The sy1xx SoC enabled CONFIG_RISCV_SOC_EXCEPTION_FROM_IRQ and provided
its own __soc_is_irq implementation. However, the behavior matches the
default implementation, making the override unnecessary.
This commit removes the custom implementation and disables the config
option to remove unnecessary code.
Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
The __soc_is_irq function is only used when
CONFIG_RISCV_SOC_EXCEPTION_FROM_IRQ is enabled, which is not the case
for any WCH SoC. The implementation is therefore dead code.
Additionally, the implementation matches the default fallback behavior,
so no functional change would occur even if the config were enabled.
Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
Add a padding section after the final read only data section
to avoid overlap between ROMABLE_REGION and RAMABLE_REGION.
Signed-off-by: Ha Duong Quang <ha.duongquang@nxp.com>
- The compatible name is the same as used in Linux kernel
- It is the watchdog timer used in K3 generation of processors.
Signed-off-by: Ayush Singh <ayush@beagleboard.org>
Zephyr is swapping the definitions of RGB565 and BGR565. Swap the return
values provided by this driver for supported pixel formats to account
for this.
Signed-off-by: Daniel DeGrasse <ddegrasse@tenstorrent.com>
This reverts the workaround made in the commit:
772fbfe9cc
as the proper fix has now been merged upstream.
Signed-off-by: Phi Bang Nguyen <phibang.nguyen@nxp.com>
Some systems (IE cores with bootloaders) may not disable the DW SPI
peripheral at boot time. Make sure the peripheral is disabled before we
try to configure it.
Signed-off-by: Daniel DeGrasse <ddegrasse@tenstorrent.com>
The designware controller has an *interesting* implementation of the CS
signal- CS will be de-asserted whenever the TX FIFO is empty, so slower
cores may see CS de-assert prematurely if they cannot keep pace with
their SPI peripheral. To help reduce odds of de-assertion, implement the
following changes:
- don't write SER bit until directly before we enable interrupts, so
that transfers don't start early
- prefix the TX FIFO before writing SER, so the FIFO can drain a bit
before have to service an interrupt
Signed-off-by: Daniel DeGrasse <ddegrasse@tenstorrent.com>
The SSI DW peripheral supports an RX_SAMPLE_DLY register in some
instances- this register controls the number of clock cycles from the
default sample time before the RX input is actually sampled. This can be
used to improve reliability when operating the SSI at a higher clock
speed.
Add an implementation of the mspi_timing_cfg api, and header to define
the identifier so that users can configure this parameter
Signed-off-by: Daniel DeGrasse <ddegrasse@tenstorrent.com>
Bitmask offsets for the MSPI_DW peripheral are incorrect for the
4.03a databook for the DW APB SSI. Add a "v2" compatible to handle these
changed offsets. The compatible does not define new binding properties,
just modifies the register offsets.
Additionally, handle writing the DFS32 mask for v2 of this compatible,
as newer IP supports a dataframe size up to 32 bits.
Signed-off-by: Daniel DeGrasse <ddegrasse@tenstorrent.com>
Multilevel interrupts require that the irq number be read with DT_IRQN,
so update the driver to use this macro.
Signed-off-by: Daniel DeGrasse <ddegrasse@tenstorrent.com>
The remainder of this driver functions when pin control is disabled,
so make the include conditional as well to fully support this case.
Signed-off-by: Daniel DeGrasse <ddegrasse@tenstorrent.com>
Supply empty vendor specific macros for cases where vendor specific
functions are not needed by driver.
Signed-off-by: Daniel DeGrasse <ddegrasse@tenstorrent.com>
USB support was previously introduced for the max32 soc family on the
max32690evkit board; this change extends that support to two additional
boards with the same soc: apard32690 and max32690fthr.
Signed-off-by: Maureen Helm <maureen.helm@analog.com>
Fixes a flaw in implementations of arch_is_in_isr() that could manifest
on SMP systems. If the reading of the current CPU's nested interrupt
count is not fully atomic on an SMP system, then an ill-timed context
switch could occur leaving the caller reading the nested interrupt
count of a different CPU.
This also applies a little defensive programming to cortex_a_r's
arch_is_in_nested_exception(). Although this routine is presently
only called with interrupts locked (which will prevent the thread
from migrating), switching to use _current_cpu instead of
arch_curr_cpu() is safer as should the routine ever be called
without meeting the locking criteria, it can be detected and fixed.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
Fixes a flaw in the the xtensa implementation of arch_is_in_isr()
that could manifest on SMP systems. If the reading of the current
CPU's nested interrupt count is not fully atomic on an SMP system,
then an ill-timed context switch could occur leaving the caller
reading the nested interrupt of a different CPU.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
Add a simple sample that tests the functionality of the EXT2 automount
feature. The sample creates a ramdisk and writes some content and tries
to read it back after unmount and mount operation.
Signed-off-by: Bas van Loon <bas@arch-embedded.com>
Device tree and/or automount support was not present and might be useful
when for example the settings module needs early access to a filesystem.
This patch adds support to mount an EXT2 filesystem automatically. The
implementation chosen is to provide the drive name matching a disk
drive specified in the device tree ie on an (e)MMC or SD card.
Signed-off-by: Bas van Loon <bas@arch-embedded.com>
The CRC32 table only needs to be generated once, so prevent it from
regenerating every time as it only required once.
Signed-off-by: Bas van Loon <bas@arch-embedded.com>
The "spacecubics" entry was redundant as we use the "sc" prefix for Space
Cubics, Inc.
Removing this duplicate to avoid confusion and maintain consistency in
vendor naming.
Signed-off-by: Gaetan Perrot <gaetan.perrot@spacecubics.com>
ZMS does not work without this and gives compilation errors, fix
this by adding the correct dependency
Signed-off-by: Jamie McCrae <spam@helper3000.net>
In the metadata, found that timer_status_sync_pending was missing the
timeout parameter. Noticed when tracing tests/kernel/common.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
In a096b34835 which introduced tracing of k_sleep, the events in the
metadata file were missed causing issues when running with babeltrace.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add details on series supported by Noritake Itron driver.
Upon reading datasheets, series CU-TE, CU-Y, GU-3000, GU-7000 and
GU-D have commands matching the driver, whereas series CU-U, CU-TW,
and GU-800 use different command sets.
Signed-off-by: Eve Redero <eve.redero@gmail.com>
Throughputs achieved by the sample are a bit better with timeslicing
disabled, therefore disable it for best out-of-the-box experience.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
The codec configuration operation for unicast (ASCS) contain
both a target PHY and a target latency value that was previously
just hardcoded by the client and unavailable by the server.
This commit adds them to the bt_audio_codec_cfg struct so that
applications can both set and get these values.
The default values used by BT_AUDIO_CODEC_CFG use the same
values as the client would previously set.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
This enables applications to call timing configuration functions,
which enables more applications to work on native_sim.
Signed-off-by: Dmitrii Sharshakov <d3dx12.xx@gmail.com>
Adds fixes to get LLEXT tests to work for NSIM VPX on MWDT.
Excludes prelocated extensions for MWDT for now.
Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
Splits LLEXT static heap into an instruction heap placed in
instruction memory and a data heap placed in data memory.
Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
Allow users to compile LLEXTs with the MetaWare Design Toolchain.
Provides utility to dramatically shrink bloated extensions by removing
unused section names left behind by MWDT strip. Test extensions will
not fit in NSIM VPX5 memory otherwise; each is reduced from ~16k to ~1k.
Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
Adds a missing requirement from Core Spec V6.0 Vol 3.A chapters 10.1
and 10.2 to ignore L2CAP_FLOW_CONTROL_CREDIT_IND packets with the
credit value set to 0.
Matches existing credit-related functions by checking that the CID
is in the dynamic range (you can't add credits to fixed channels).
Signed-off-by: Håvard Reierstad <haavard.reierstad@nordicsemi.no>
