The Zephyr network interface should not be disabled by the USB device
functions. This sounds confusing, but in the current implementation they
are different ends of the connection.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
We need to handle notifications periodically, for example, when the
interface alternate changes and we also need to track whether the
notification was actually transfered to the host. There is no need to
trigger notification work on iface_start/iface_stop when the USB
interface is not in active configuration. This commit intentianly
changes log level in the notification handling code.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
In the current implementation, the block length in the OUT direciton
should be equal to the transfer length.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
The implementation should not assume that NDP is placed immediately
after NTH. According to the specification (revision 1.0), NDP can be
anywhere in the transfer buffer. There is also always a "terminating
zero datagram pointer entry", which we should also use to terminate the
datagram processing loop.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Use STM32_CLOCK() clock select macro with bit-25
set.
This change shall set register RCC_CCIPR->FDCANSEL
to 0x01.
Previosuly there were bit-12 set, which was wrong.
For more information refer to RM0440 Rev. 8
page 323 of 2138.
Signed-off-by: Alexander Kozhinov <ak.alexander.kozhinov@gmail.com>
In nRF53 SoC, the CPUAPP owns all the GPIOs by default.
Therefore, even if the GPIOs are exclusively used by CPUNET,
we must redefine them for CPUAPP and then set up GPIO
forwarding to CPUNET using SoC registers (this is done as
part of the MPSL CX initialization).
Previously, these GPIOs were mistakenly removed from CPUAPP
and defined only for CPUNET. This caused the GPIOs to be
available for CPUNET but still owned by CPUAPP, breaking
SR coexistence.
Signed-off-by: Murali Thokala <Murali.Thokala@nordicsemi.no>
Introduce Google Icetower Development Board.
Icetower is a board created by Google for fingerprint-related
functionality development.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
For some stm32 devices, especially the stm32H7RS serie,
the RCC register map is larger that 256 (example AHB1 is 0x138).
The mask is extended to 0x1ff in the .bus of the clock info structure,
using the GENMASK macro from STM32_CLOCK_DIV_SHIFT
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Fixes an issue introduced with commit
c6ad4a7927 which wrong restarts
advertising after a device connects when it should only restart
advertising if a device fails to connect
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Renames the blob cli bounds command to blob cli caps in documentation,
matching the implementation in shell.
Signed-off-by: Håvard Reierstad <haavard.reierstad@nordicsemi.no>
Rename everything from tla2021 to tla202x (except dtcompatible)
in preparation to add support for tla2022 and tla2024
Signed-off-by: Benjamin Bigler <benjamin.bigler@securiton.ch>
Currently, there is a small race window where we can miss an interrupt.
Right after we're done reading the RX buffer but just before decrementing
the RX counter to zero, the ENC28J60 may receive a packet. The chip will
raise an interrupt, but the line is still asserted. That means that the
callback will not be invoked since it is edge-triggered.
To avoid that, disable interrupts on the chip itself before processing
the RX buffer.
In fact, the ENC28J60 datasheet specifically says:
"After an interrupt occurs, the host controller should
clear the global enable bit for the interrupt pin before
servicing the interrupt. Clearing the enable bit will
cause the interrupt pin to return to the non-asserted
state (high). Doing so will prevent the host controller
from missing a falling edge should another interrupt
occur while the immediate interrupt is being serviced.
After the interrupt has been serviced, the global enable
bit may be restored. If an interrupt event occurred while
the previous interrupt was being processed, the act of
resetting the global enable bit will cause a new falling
edge on the interrupt pin to occur."
This is also what is being done in the Linux driver [1].
[1] https://elixir.bootlin.com/linux/v6.11.2/source/drivers/net/ethernet/microchip/enc28j60.c#L1126
Signed-off-by: Xavier Ruppen <xruppen@gmail.com>
The enc28j60 errata sheet says:
"The Receive Packet Pending Interrupt Flag
(EIR.PKTIF) does not reliably/accurately report
the status of pending packets."
"In the Interrupt Service Routine, if it is unknown if
a packet is pending and the source of the interrupt
is unknown, switch to Bank 1 and check the value
in EPKTCNT.
If polling to see if a packet is pending, check the
value in EPKTCNT."
A workaround has already been implemented inside of eth_enc28j60_rx().
But checking PKTIF before calling eth_enc28j60_rx() completely defeats
the purpose of the workaround. Do not check it.
Moreover, clearing ENC28J60_BIT_EIR_PKTIF is useless since it is
automatically cleared once all packets are read. So remove that check
and clarify comment.
Also please refer to the Linux driver [1].
[1] https://elixir.bootlin.com/linux/v6.11.2/source/drivers/net/ethernet/microchip/enc28j60.c#L1090
Signed-off-by: Xavier Ruppen <xruppen@gmail.com>
After a non-power reset (wdt) pins may remain in non-default state.
To ensure that a system initialization is the same after any reset,
it is necessary to initialize pins to the default state.
Signed-off-by: Mikhail Siomin <victorovich.01@mail.ru>
Enable CONFIG_HAS_MCUX_IGPIO because device driver CONFIG_GPIO_MCUX_IGPIO
depends on it, so that the driver can be enabled by dts nodes.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Map MMIO memory by using DEVICE_MMIO_NAMED_x() APIs.
And some platforms has no soc.h, so use __has_include to check it
firstly.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Mark the I2C instances as `PM_DEVICE_ISR_SAFE`, as the transition
operations are short, it saves RAM resources, and the spin-locking fixes
the non-atomic behaviour of the PM usage counter.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Fixes issue where function returns being used as data arguments to
k_fifo tracing macros were being called mulitple times due to
preprocessor copying macro arguments during expansion.
Signed-off-by: Anthony Williams <anthony289478@gmail.com>
Enhance the driver to calculate the L2 cache line size and number
of ways at runtime. The L2 cache line size is assumed to match
the L1 cache line size, while the number of ways is determined
based on the total L2 cache size.
Signed-off-by: Wei-Tai Lee <wtlee@andestech.com>
Add max22190 gpio driver with input functionality, since device
support only input without output.
Implemented diagnostic functionality for all 8 channels
which include various check to over/under voltage and wire break.
Filtering configuration is done from devicetree on per channel
bases and is configured on chip start.
In case some fault condition occure FAULT pin drive LOW which
prop to FAULT registers to be read. Data is stored in data structure
for furter analizes and ERR message is printed in console.
Signed-off-by: Stoyan Bogdanov <sbogdanov@baylibre.com>
It reports Advanced Pedometer and Event Detection features,
such as Pedometer, Tilt detection, Wake on Motion and
Significant Motion Detector. Device tree options.
Signed-off-by: Aurelie Fontaine <aurelie.fontaine@tdk.com>
Add the power mode, accel and gyro filtering options,
and apex features. Add -p and -s compatible.
Signed-off-by: Aurelie Fontaine <aurelie.fontaine@tdk.com>
Prepare to use official TDK Invensense Inc. driver for icm42670-P/-S
sensor in tdk_hal module. Simplify I2C and SPI transport files.
Driver code moves in hal_tdk module.
Adds APEX features, such as Pedometer, Tilt detection, Wake on Motion
and Significant Motion Detector.
Signed-off-by: Aurelie Fontaine <aurelie.fontaine@tdk.com>
Add Toradex Verdin iMX8M Mini board based on NXP MIMX8MM EVK using the
i.MX8MM SoC. This code is intented to be used with the Cortex-M4.
Signed-off-by: Hiago De Franco <hiago.franco@toradex.com>
