Some flash devices enable entering the 4-byte address mode
by setting BIT(7) in a special register via a write instruction 0x17.
The support for this method is indicated in BIT(3) of
Enter 4-Byte Addressing byte in 16th DWORD of the JEDEC Basic
Flash Parameter Table.
Infineon's S25FL512S is an example flash device with this feature.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
The SoC State Change Power Domain driver issues TURN_ON/
TURN_OFF actions to all devices registered with it for
certain power states that can be specified via device tree.
This test exercises the functionality of this driver.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
This driver triggers the TURN_ON and TURN_OFF actions for certain
power states. These power states are specified via device tree.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
This commit adds a missing default value for the `DCHACHE_LINE_SIZE` option
for the `qemu_xtensa/sample_controller32/mpu` platform. This is required
after 8b39d4a613 added a build assert
checking this value against `core-isa.h` from Xtensa HAL.
Fixes#85591.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Update the HW models module to:
5dc34b26662c6ec91edf1174d775d78590b1a05b
Including the following:
* 5dc34b2 CLOCK (52-54): Silly bugfix
* 4f622b7 CLOCK (52-54): Make TASK_*CLKSTOP instantaneous and clear
LFCLK.STAT
* 07b1bdb RADIO 54: Correct 2 comments related the CCM trigger
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Taking a look at the schematic shows that
tx-enable-gpios and dio2-tx-enable were directly connected.
This had the effect tx-enable-gpios was trying to pull the line down
while SX1262 is pulling the same line high. This increased
the power consumption.
Now only the SX1262 sets the antenna to tx via dio2-tx-enable.
Setting the antenna to rx is still done via the rx-enable-gpios.
The antenna defaults to rx if not in use.
Signed-off-by: Carlo Weidinger <carlo.weidinger@protonmail.com>
Enable wdt_error_cases test on nRF5340dk.
Define valid test configuration for that target
(reuse from nRF54H/nRF54L).
Add target to the platform_allow.
Signed-off-by: Sebastian Głąb <sebastian.glab@nordicsemi.no>
Add UART test overlays for Nucleo N657x0-Q and STM32N6570 DK boards.
Remove non serial boot conf file since they are now unnecessary.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Due to the added demos, a memory pool of 49 KiB is no longer enough and
leads to crashes:
https://github.com/lvgl/lvgl/issues/7648
Increasing the memory pool to 57 KiB fixes the problem.
Signed-off-by: Detlev Zundel <dzu@member.fsf.org>
There were some compilation errors caused by unused functions.
Add proper #ifdef statements not to include unused functions.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
When TRDC permission fails to be obtained, it does not recycle to
access ELE core to prevent blocking problems. The current practice
only generates a log warning alarm.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
silabs_s2 uses simplicity_sdk hal library, which already have by default
a zero latency IRQs mechanism with a hardcoded value. In order to be
aligned with simplicity_sdk, we need to activate Zero Latency IRQ in
Zephyr by default. The level (2) depends on the hardcoded
value in simplicity_sdk (CORE_ATOMIC_BASE_PRIORITY_LEVEL). Without this
fix, if you use an IRQ with a priority of 0 or 1, irq_lock() and
irq_unlock() have no effect for this IRQ.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Add Clock Control support for board RZ/G3S-SMARC
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Add Clock Control driver support for Renesas RZ/G3S
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
In the current implementation, when `gpio_ra_pin_interrupt_configure`
is executed, the existing settings made by `gpio_ra_pin_configure`
are erased.
A read-modify-write method will be used to preserve the settings.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
@ithinuel will be continuing to help with reviews on
Arm and Arm64 arch/platform so adding him as collaborator.
Also adding me @wearyzen as collaborator for Arm64 to
help with reviews.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
Building with clang warns:
drivers/sensor/st/ism330dhcx/ism330dhcx.c:107:19: error: unused function
'ism330dhcx_reboot' [-Werror,-Wunused-function]
static inline int ism330dhcx_reboot(const struct device *dev)
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Building with clang warns:
drivers/dma/dma_emul.c:73:20: error: unused function
'dma_emul_xfer_is_error_status' [-Werror,-Wunused-function]
static inline bool dma_emul_xfer_is_error_status(int status)
^
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
This SoC has an external XCACHE controller for CPU0
instruction and data bus.
Add code to enable the data cache. Instruction cache
is already enabled by SystemInit.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
When using the interrupt UART API, it is expected that the driver will
call the callback function repeatedly while TX interrupt is enabled.
However that is not necessarily the case with the FIFO is enabled.
If the application calls uart_fifo_fill() each time with only one byte
of data, the TX interrupt will never trigger. This is because the 1/8 TX
interrupt trigger threshold is never reached. For this reason, the
callback function should be called multiple times from software as
needed.
Fixeszephyrproject-rtos/zephyr#85479
Signed-off-by: Xudong Zheng <7pkvm5aw@slicealias.com>
