Fix STM32 WBA and H7 clock drivers to release the reference counter
added to access LSE configuration controllers once the clock is
configured. Keeping such an unbalanced access request is no more
needed since SoC functions manage reference counting of access requests.
Fixes issue 90942.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Use recently added SoCs functions to request access to SoC backup
domain resources These function use a reference counter to track these
request and ensure the resources are accessible as long as at least a
consumer requires access.
By the way, correct stm32_hsem.h header file inclusion that requires
brackets (<>) delimiters, not double quotes, as per convention on header
location.
Fixes issue 90942.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Use recently added SoCs functions to request access to SoC backup
domain resources These function use a reference counter to track these
request and ensure the resources are accessible as long as at least a
consumer requires access.
By the way, move inclusion of stm32_hsem.h header file after inclusion
of the LL header files and Zephyr header standard files.
Fixes issue 90942.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Use recently added SoCs functions to request access to SoC backup
domain resources These function use a reference counter to track these
request and ensure the resources are accessible as long as at least a
consumer requires access. When we're done accessing RTC registers and
other protected resource, release the access refcount.
By the way, simplify rtc_stm32_read() when COUNTER_NO_DATE is defined
that used a useless extra local variable.
By the way, correct stm32_hsem.h header file inclusion that requires
brackets (<>) delimiters, not double quotes, as per convention header
location.
Fixes issue 90942.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Use recently added SoCs functions to request access to SoC backup
domain resources These function use a reference counter to track these
request and ensure the resources are accessible as long as at least a
consumer requires access.
Fixes issue 90942.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Use recently added SoCs functions to request access to SoC backup
domain resources These function use a reference counter to track these
request and ensure the resources are accessible as long as at least a
consumer requires access.
Fixes issue 90942.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Add SoC functions to enable/disable STM32 backup Domain access
and use a reference counter to track requests. These helper functions
may be called from a interrupt context. On domain access enable, the
function loops until written bit is set however this is expected to be
effective after very few clock cycles and seems not even required
(not mentioned in any SoC documentation). The loop is preserved as
used in previous implementation.
Among all supported STM32 SoCs, only STM32C0 and STM32WB0 series do not
implement this mechanism hence add option CONFIG_STM32_BACKUP_PROTECTION
that is enabled for all SoC series but these 2.
Fixes issue 90942.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Update with the latest nordic hal which includes an updated
CRACEN driver which supports the 54LM20 and newer devices
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Updated documentation to clarify that while credential pairs should
generally share the same secure tag for subsystems supporting multiple
credentials per tag, some implementations may expect only one credential
per tag.
Signed-off-by: Maxwell Weru <mburumaxwell@gmail.com>
...when FIFO is empty"
This reverts commit 47e43d552e.
This is breaking sample.sensor.shell.pytest where characters
are either missing or repeated when printing to the console.
Originally this is just for RISC-V with PLIC interrupt
controller. That was made more general to avoid having arch
specific code in a generic driver. And now it is breaking
on non-RISC-V platforms. Note that the QEMU RISC-V boards
all have PLIC as interrupt controller and are passing sensor
shell pytest without this workaround. So this does not seem
to be an issue with PLIC and NS16550. So revert the commit
for now.
Fixes#92187
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add support for the stlink_gdbserver runner to the aforementionned board.
Update the "Debugging" section of the board documentation accordingly,
along with cleaning up the existing text.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Add support for the stlink_gdbserver runner to the aforementionned board.
Update the "Debugging" section of the board documentation accordingly,
along with cleaning up the existing text.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
When try to set twt, system will try to
get interface status firstly.
In shim driver, miss filling twt_capable field.
The twt_capable is set as false by default.
Failed to set twt because of incorrect
twt_capable.
Add enhance code to fill twt_capable field
in shim driver.
Signed-off-by: Qiankun Li <qiankun.li@nxp.com>
With the current configuration, we encounter a user setting error
during the test with the log:
"Wrong number of bytes received, got: 2, expected: 3."
Workaround:
Increase the clock frequency to enable faster data transmission
and avoid user setting errors.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
Since nucleo_f746zg has NOCACHE_MEM defined
(related to test cases drivers.uart.async_api.nocache_mem
and drivers.uart.async_api.nocache_mem_dt.nucleo_f746zg),
the TX buffer should be placed in a non-cacheable memory region
for the uart_async_var_buf_length testsuite to pass.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
Commit adds information about the removal of
the TinyCrypt crypto in Bluetooth Mesh.
Signed-off-by: Aleksandr Khromykh <aleksandr.khromykh@nordicsemi.no>
Fixes: commit 5f4b51f9b1 ("soc: intel_adsp: add a debug window slot
descriptor") - restore the maximum debug slot number. The added slot
resides in page 0, not at the end of the array. The bug didn't have
any run-time implications - no access to those high index value slots
is performed, all platforms so far have 3 slots at most, so this is a
pure correctness fix.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Previously, zms_read() could fill the buffer up to sizeof(rdname),
leaving no space for the null terminator, which could cause an
out-of-bounds write.
This change reduces the read size to sizeof(rdname) - 1 and appends
a '\0' manually, ensuring the buffer is always null-terminated safely.
Fixes: CID 516244
Fixes: #90533
Signed-off-by: sudarsan N <sudarsansamy2002@gmail.com>
Add Renesas RA board support for these tests:
- tests/drivers/i2s/i2s_api
- tests/drivers/i2c/i2c_speed
Signed-off-by: Khoa Tran <khoa.tran.yj@bp.renesas.com>
Size given to __aligned() is in bytes.
Align following DCACHE line size, or default to 32-byte alignment
Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
implements option to enable double endpoint buffer to improve throughtput
for non-control endpoints.
Signed-off-by: Chew Zeh Yang <zeon.chew@ambiq.com>
Add USB node to apollo510 qualifier, and apollo510_evb board to enable
USB support on the SoC and its EVB.
Signed-off-by: Chew Zeh Yang <zeon.chew@ambiq.com>
Fix issues that Renesas RZ boards cannot run the below serial
samples properly with sci and scif.
- `samples/subsys/console/echo`
- `samples/subsys/shell/shell_module`
The modification is to make the callback invoked in tei interrupt.
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
This demonstrates the ADC driver added in the previous commit. The
sample reads A0 as well as two built-in channels - one that reports
the internal 1.2 reference volatage and one that reports half the
analog supply voltage.
Signed-off-by: Michael Hope <michaelh@juju.nz>
The CH32V003 has a 8 channel, 10 bit onboard ADC. Add an immediate
mode driver and the appropriate pinctrl bindings. Note that the
CH32V003 GPIO pins have both a floating input and an analogue input
mode, and the pinctrl is needed to put the pin in analogue mode.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Due to a BootROM clock switching issue, XSPI1 should use HCLK otherwise
app won't restart on reset.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Make axisram2 which is used in fsbl mode available as well to
chainloaded application in order not to loose 1M of RAM
In order to avoid conflicts with bootloader, verify that code + ro data
of the loaded application won't go further than bootloader start address.
This is done with a linker assert.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
