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Author SHA1 Message Date
Furkan Akkiz
185f328135 tests: drivers: dma: Add MAX32690 overlay files 
Enable 'chan_blen_transfer' and 'loop_transfer' tests for MAX32690EVKIT.

Co-authored-by: Maureen Helm <maureen.helm@analog.com>
Signed-off-by: Furkan Akkiz <hasanfurkan.akkiz@analog.com>
 2024-08-06 17:16:35 -04:00
Sadik Ozer
3a7260dab3 tests: drivers: dma: Add MAX32655 board overlay files 
Add MAX32655EVKIT and FTHR board overlay files to dma tests.

Co-authored-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Co-authored-by: Maureen Helm <maureen.helm@analog.com>
Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
 2024-08-06 17:16:35 -04:00
Furkan Akkiz
c7ea289ea2 boards: arm: adi: Add DMA to MAX32690EVKIT board driver list 
Add DMA into 'index.rst' and '.yaml' files.

Signed-off-by: Furkan Akkiz <hasanfurkan.akkiz@analog.com>
 2024-08-06 17:16:35 -04:00
Tahsin Mutlugun
0c6342e36b boards: arm: adi: Add DMA to MAX32680EVKIT board driver list 
Add DMA into 'index.rst' and '.yaml' files and enable dma0 instance.

Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
 2024-08-06 17:16:35 -04:00
Furkan Akkiz
aac7c09cb7 boards: arm: adi: Add DMA to MAX32672 boards driver list 
Add DMA into 'index.rst' and '.yaml' files.

Signed-off-by: Furkan Akkiz <hasanfurkan.akkiz@analog.com>
 2024-08-06 17:16:35 -04:00
Mert Ekren
8819180c48 boards: arm: adi: Add DMA to MAX32670EVKIT board driver list 
Add DMA into 'index.rst' and '.yaml' files.

Signed-off-by: Mert Ekren <mert.ekren@analog.com>
 2024-08-06 17:16:35 -04:00
Jason Murphy
fb1fb2747c boards: arm: enable DMA on MAX32655 boards 
Enable DMA peripheral support on MAX32655EVKIT and FHTR boards.

Co-Authored-By: Sadik Ozer <sadik.ozer@analog.com>
Signed-off-by: Jason Murphy <jason.murphy@analog.com>
 2024-08-06 17:16:35 -04:00
Jason Murphy
364af34de0 drivers: dma: Add MAX32655 DMA driver 
Add DMA driver for MAX32655 MCU

Co-authored-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Signed-off-by: Jason Murphy <jason.murphy@analog.com>
 2024-08-06 17:16:35 -04:00
Tahsin Mutlugun
910d88741a dts: arm: adi: Add MAX32680 DMA instance and binding file 
Add DMA0 node to MAX32680 dtsi file and add binding file for DMA slots.

Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
 2024-08-06 17:16:35 -04:00
Furkan Akkiz
b64c0b829a dts: arm: adi: Add MAX32672 DMA instance and binding file 
Add DMA0 node to MAX32672 dtsi file and add binding file for DMA slots.

Signed-off-by: Furkan Akkiz <hasanfurkan.akkiz@analog.com>
 2024-08-06 17:16:35 -04:00
Mert Ekren
fd52e38aef dts: arm: adi: Add MAX32670 DMA instance and binding file 
Add DMA0 node to MAX32670 dtsi file and add binding file for DMA slots.

Signed-off-by: Mert Ekren <mert.ekren@analog.com>
 2024-08-06 17:16:35 -04:00
Furkan Akkiz
53cb59cfc4 dts: arm: adi: Add MAX32690 DMA instance and binding file 
Add DMA0 node to MAX32690 dtsi file and add binding file for DMA slots.

Signed-off-by: Furkan Akkiz <hasanfurkan.akkiz@analog.com>
 2024-08-06 17:16:35 -04:00
Sadik Ozer
def2dcb70b dts: arm: adi: max32: Add MAX32 DMA driver bindings 
Add MAX32 DMA driver bindings and DMA instance for MAX32655 MCU.

Co-authored-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
 2024-08-06 17:16:35 -04:00
Pisit Sawangvonganan
253d216589 net: ip: utils: revise data type declarations in z_impl_net_addr_ntop 
Revise data type declarations to avoid implicit/explicit casts:
- Changed `unsigned char` to `uint8_t` for `zeros` array
  to match with `longest`.
- Declared variables `i`, `j`, and `pos` as `int` to use the same type.
- Cast `value` to `uint16_t` instead of `uint32_t` since
  `value` is `uint16_t`.
- Moved `bh` and `bl` declarations to narrow the scope of variables.

Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
 2024-08-06 17:15:50 -04:00
Pisit Sawangvonganan
71877efe27 net: ip: utils: simplify logic in z_impl_net_addr_ntop 
Simplify high and low byte conversion by removing redundant checks,
since `net_byte_to_hex` already takes care of zero padding.

Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
 2024-08-06 17:15:50 -04:00
Pisit Sawangvonganan
dd864dbda0 net: ip: utils: simplify logic in net_byte_to_hex 
Replace the loop with direct high and low nibble extraction,
and ensure the padding and zero suppression logic is simplified.

Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
 2024-08-06 17:15:50 -04:00
Tobias Frauenschläger
f4202faad5 Add: Support for pyOCD for STM32H43 nucleo board 
Updated `board.cmake` and documentation.

Signed-off-by: Tobias Frauenschläger <t.frauenschlaeger@me.com>
 2024-08-06 17:15:34 -04:00
Roman Studenikin
edf09ca7f9 testsuite: coverage: Correct value of GCOV_COUNTERS for gcc 14 
number of counters have changed in gcc 14 by commit
08a5233180

Specifically, a new counter was added in gcc/gcov-counter.def:
```
/* Conditions.  The counter is interpreted as a bit-set.  */
DEF_GCOV_COUNTER(GCOV_COUNTER_CONDS, "conditions", _ior)
```

which in turn updates the value of GCOV_COUNTERS that is defined in
gcov-io.h like this:
```
enum {
GCOV_COUNTERS
};
```

Signed-off-by: Roman Studenikin <srv@meta.com>
 2024-08-06 17:15:22 -04:00
Nicolas Pitre
be119d7d8c demand_paging: LRU eviction: avoid ping pong deadlock loop 
If only 2 page frames are queued and code executing in one frame is
making an access to memory in the second frame then the access will trap
and k_mem_paging_eviction_accessed() will be called to move that frame
to the end of the queue ... marking the new head frame unaccessible.
But that newly unaccessible frame contains the code that has yet to be
resumed to perform its memory access. Since it is now unaccessible, a
trap is triggered, the frame is moved to the end of the queue and the
new head frame (the one we trapped for initially) is marked unaccessible.
Execution is resumed with the memory access which is unaccessible again
and the cycle repeats infinitely.

Fix this by not marking the new head unaccessible if there is only one
queued frame left in the queue.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
 2024-08-06 17:15:15 -04:00
Richard Wheatley
f36bd0a075 tests: drivers: rtc: rtc_api: test_update_callback 
Add skip for when no update callback is defined
in driver

Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
 2024-08-06 17:14:39 -04:00
Arkadiusz Balys
2de6274119 drivers: flash: Do not select NRFX_RRAMC while building with TF-M 
RRAMC peripheral is a secure-only peripheral, and the application
cannot use it directly. While building an application with TF-M
enabled and SOC_FLASH_NRF_RRAM the NRFX_RRAMC selection must
be forbidden.

Signed-off-by: Arkadiusz Balys <arkadiusz.balys@nordicsemi.no>
 2024-08-06 15:42:44 +01:00
Anas Nashif
edb71f0ba1 manifest: add mcuboot to bootloader group 
Add mcuboot to bootloader group to allow filter where needed.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
 2024-08-06 08:47:01 -04:00
Anas Nashif
a9babb5a83 twister: tests: use platforms that do not depend on a HAL 
Do not depend on platforms that need a HAL. This should speed things up
and should resolve issues where runner did not have enough space to deal
with all HALs.
t
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
 2024-08-06 08:47:01 -04:00
Anas Nashif
4f60d593f3 ci: twister: blackbox: do not fetch optional modules 
Do not fetch optional modules while running this action.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
 2024-08-06 08:47:01 -04:00
Gerard Marull-Paretas
ec95cbb74a samples: drivers: mbox: add support for nrf54h20dk cpuapp<>cpuflpr 
Add support for testing IPC between cpuapp<>cpuflpr. Some adjustments
have been done to be able to support two different remote targets for
the nrf54h20dk cpuapp.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
 2024-08-06 14:32:40 +02:00
Gerard Marull-Paretas
85fb9db4c3 samples: sysbuild: hello_world: add cpuapp/cpuflpr+xip configuration 
So that xip board variant can be easily tested.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
 2024-08-06 14:32:40 +02:00
Gerard Marull-Paretas
2f399b8896 samples: sysbuild: hello_world: add cpuapp/cpuflpr configuration 
So that a hello world that runs on cpuapp/cpuflpr cores can be easily
tested.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
 2024-08-06 14:32:40 +02:00
Gerard Marull-Paretas
8dcc2e05cc snippets: nordic-flpr-xip: add support for nrf54h20dk 
Add support for nRF54H20.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
 2024-08-06 14:32:40 +02:00
Gerard Marull-Paretas
3bf9e84ddc snippets: nordic-flpr-xip: move vevif enablement to nRF54L15DK overlay 
Other platforms, e.g. nRF54H20 do not need this.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
 2024-08-06 14:32:40 +02:00
Gerard Marull-Paretas
d9fc08eca4 snippets: nordic-flpr: add support for nrf54h20dk 
Provide overlay to mark uart135 as reserved (used by FLPR).

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
 2024-08-06 14:32:40 +02:00
Gerard Marull-Paretas
7f49621131 snippets: nordic-flpr: move vevif enablement to nRF54L15DK overlay 
Other platforms using FLPR, e.g. nRF54H20 do not need this.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
 2024-08-06 14:32:40 +02:00
Gerard Marull-Paretas
371acf4ea4 boards: nrf54h20dk: add xip variant for cpuflpr 
While executing from MRAM will likely never happen in practice for the
FLPR core, add such variant for testing.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
 2024-08-06 14:32:40 +02:00
Gerard Marull-Paretas
e290dfe399 boards: nrf54h20dk: add cpuflpr target 
Add a new board target to build for the FLPR core.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
 2024-08-06 14:32:40 +02:00
Gerard Marull-Paretas
beb5d72548 boards: nrf54h20dk: add cpuapp/cpuflpr IPC configuration 
Add IPC configuration to allow communicating between cpuapp and cpuflpr
cores.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
 2024-08-06 14:32:40 +02:00
Gerard Marull-Paretas
dd58aa1351 boards: nrf54h20dk: add FLPR code partition in MRAM1X 
Add a new 48K partition for FLPR in the MRAM1X region.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
 2024-08-06 14:32:40 +02:00
Gerard Marull-Paretas
6ba48daa6e boards: nrf54h20dk: shrink cpuapp slot0 partition 
So that we have an extra 48K for the FLPR core.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
 2024-08-06 14:32:40 +02:00
Gerard Marull-Paretas
9e7b055f63 boards: nrf54h20: define FLPR memory layout within RAM21 region 
Define the FLPR memory layout:

- 46K for code data
- 1K/1K for IPC between cpuapp/cpuflpr

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
 2024-08-06 14:32:40 +02:00
Gerard Marull-Paretas
d838a1f069 boards: nrf54h20dk: push dma_fast_region area to the end of the region 
So that we can use the first 48K for FLPR.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
 2024-08-06 14:32:40 +02:00
Gerard Marull-Paretas
00ed91fb94 modules: hal_nordic: add support for nRF54H20 FLPR 
Add necessary HAL glue code to support nRF54H20.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
 2024-08-06 14:32:40 +02:00
Gerard Marull-Paretas
4bc55acaff soc: nordic: vpr: allow building VPR launcher for FLPR 
VPR launcher can also be used for FLPR.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
 2024-08-06 14:32:40 +02:00
Gerard Marull-Paretas
3f3ffb91ad soc: nordic: nrf54h20: define CPUFLPR core 
So that FLPR core can be used.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
 2024-08-06 14:32:40 +02:00
Gerard Marull-Paretas
009f3e3669 dts: riscv: nordic: nrf54h20: introduce cpuflpr 
Add a new base devicetree file for the FLPR core.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
 2024-08-06 14:32:40 +02:00
Gerard Marull-Paretas
c2ddba98a0 dts: nordic: nrf54h20: define cpuflpr VEVIF TX instance 
Define the FLPR VEVIF instance (used to send _tasks_).

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
 2024-08-06 14:32:40 +02:00
Gerard Marull-Paretas
d8c84309e0 dts: nordic: nrf54h20: define cpuflpr VEVIF RX instance 
Define the FLPR VEVIF instance (used to receive _tasks_).

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
 2024-08-06 14:32:40 +02:00
Gerard Marull-Paretas
d77ee01d10 dts: nordic: nrf54h20: define FLPR CLIC instance 
Define the FLPR CLIC instance.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
 2024-08-06 14:32:40 +02:00
Gerard Marull-Paretas
b5522411e3 dts: nordic: nrf54h20: define cpuflpr_vpr coprocessor 
Add a new entry for the FLPR co-processor instance.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
 2024-08-06 14:32:40 +02:00
Gerard Marull-Paretas
d3ab37ceab dts: nordic: nrf54h20: define cpuflpr 
Define the FLPR VPR CPU instance.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
 2024-08-06 14:32:40 +02:00
Gerard Marull-Paretas
2d2db37c09 modules: hal_nordic: require nrf-regtool 5.6.0 
This is required since NRF_FUN_POS (pinctrl) has changed its position
from 17 to 18 (a value hardcoded in the nrf-regtool as well).

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
 2024-08-06 14:32:40 +02:00
Gerard Marull-Paretas
5e3188605e drivers: pinctrl: nrf: add support for nordic,clock-enable 
Driver will be capable of retrieving such property from DT and apply it
accordingly.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
 2024-08-06 14:32:40 +02:00
Gerard Marull-Paretas
b57481ab18 boards, tests: nrf54h20: add nordic,clock-enable property 
Applies to:

- UART/E (TXD)
- SPIM (SCK, MOSI)
- SPIS (SCK, MISO)
- TWIM (SDA, SCL)

Except fast-instances.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
 2024-08-06 14:32:40 +02:00