This commit updates the clang workflow to pre-clone the Zephyr
repository from the runner repository cache.
Note that the `origin` remote URL is reconfigured to that of the GitHub
Zephyr repository because the checkout action attempts to delete
everything and re-clone otherwise.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit updates the clang workflow to use the new Kubernetes-based
zephyr-runner.
Note that the repository cache directory path has been changed for the
new runner.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The repository clean-up steps are no longer necessary because the new
zephyr-runner is ephemeral and does not contain any files from the
previous runs.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit updates the twister workflow to pre-clone the Zephyr
repository from the runner repository cache.
Note that the `origin` remote URL is reconfigured to that of the GitHub
Zephyr repository because the checkout action attempts to delete
everything and re-clone otherwise.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit updates the twister workflow to use the new Kubernetes-
based zephyr-runner.
Note that the repository cache directory path has been changed for the
new runner.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
net_buf does not hold strings, it holds counted bytes. Use memcpy to place
data into the buffer during testing rather than strncpy as the latter
generates warnings because the destination will not be nul-terminated.
Signed-off-by: Keith Packard <keithp@keithp.com>
The data field is a *pointer* to the buffer, not the actual buffer itself.
Instead of smashing past the end of the struct, write through that pointer.
Signed-off-by: Keith Packard <keithp@keithp.com>
Using very old machine does not make sense anymore. Switch to the new
Q35 (https://wiki.qemu.org/Features/Q35). Among other things it allows
to test SMBus and watchdog.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Cleanup the mess of duplicate function definitions, unnecessary
variables and duplicate strings. All banner strings are now constant in
ROM. Also fixes a double space between the end of the version string and
the trailing `***` when there is no boot delay.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
The BOOT_DELAY option does nothing in code if MULTITHREADING is not
enabled. Move the dependency to Kconfig instead.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Microchip MEC172x has a modified eSPI SAF hardware implementation.
Hardware changes include multiple clock dividers for each SPI
flash device and data transfer using QMSPI local DMA.
espi reset interrupt is made a higer priority in MEC172x devicetree
because espi reset event resets all espi hardware and we don't
to want to service any other espi interrupt blocks when espi reset
occurs.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Microchip MEC172x eSPI SAF has significant hardware changes
requiring a new SAF configuration structure. In preparation
for the MEC172x we move the current SAF header out of common
to the MEC1501 subfolder, remove an unused and empty common
header and remove includes of the moved headers from MEC172x.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Set default interrupt priority to 3 for all Microchip MEC172x eSPI
host child devices except the UART's which are set to 1.
The espi peripherals don't require the maximum priority hence they
are being made uniform and a lower priority 3.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Microchip MEC172x QMSPI expanded its clock divider register
field from 8 to 16 bits. QMSPI source clock is on the fast
peripheral domain therefore get the frequency from the clock
control driver.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Microchip MEC172x CPU and fast peripheral (QMSPI and PK) are
clock source is based upon an OTP setting. Add logic to adjust
clock source based on OTP value. If the OTP value is ever changed
this fix will allow calcluation of correct clock rate.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Microchip MEC172x EVB no longer has any C files in board
folder. Remove the cmake library rule as it it causing
a build warning due to no source files.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Regexp suggested in #50173 PR is too strictly and
needs to be corrected. Previous regexp declines
engineering MWDT versions
(pattern ENG-2022.12-D1039-C39098348").
Signed-off-by: Nikolay Agishev <agishev@synopsys.com>
Both CONFIG_BIG_ENDIAN and CONFIG_LITTLE_ENDIAN can be used in the code,
so reflect that in the error message in checkpatch.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Refactor the POSIX arch documentation out of the
native_posix page into its own page.
Originally native_posix was the only POSIX arch based
board, but this has not been the case anymore for several
years.
The architecture part of the documentation being in the
native_posix doc has created uneeded confusion over time.
Both due to this, and as preparation for much more
documentation for the bsim boards, refactor it out.
This is mostly a refactoring exercise, with only very
minor changes in the text to keep it consistant with
the move.
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
Mention removal of flashdisk Kconfig options in favor of new
zephyr,flash-disk devicetree binding.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Remove all obsolete DISK_FLASH* Kconfig options.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Use devicetree to obtain information for all zephyr flash disks.
Co-authored-by: Johann Fischer <johann.fischer@nordicsemi.no>
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Add flash disk description to overlays. Specify custom flashdisk
partition for fat fs api test to match the Kconfig values, because
native posix storage partition is too small for FatFS filesystem.
Co-authored-by: Johann Fischer <johann.fischer@nordicsemi.no>
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Add bindings to describe a block storage device based on flash map
partition.
Co-authored-by: Johann Fischer <johann.fischer@nordicsemi.no>
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
In order to avoid using multiple sources of truth for the platfom's
endianness, convert the in-tree code to use the (BIG|LITTLE)_ENDIAN
Kconfig variables exclusively, instead of the compiler's
__BYTE_ORDER__.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
In preparation for using CONFIG_(BIG|LITTLE)_ENDIAN exclusively for
endianness-based conditional compilation in the tree, ensure that the
Kconfig CONFIG_(BIG|LITTLE)_ENDIAN options match the compiler's
__BYTE_ORDER__ macro.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
In preparation for using CONFIG_*_ENDIAN instead of __BYTE_ORDER__, add
a reflection of CONFIG_BIG_ENDIAN that will allow users to conditionally
compile with #ifdef instead of #ifndef while keeping the default case
(little endian) as the first block in the conditional compilation.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Store the offset of mode_exc_return in the arch struct. This is required
to restore the link register to the original value, as `swap_helper.S`
saves the LSB to this field when `CONFIG_ARM_STORE_EXC_RETURN=y`.
Failing to account for this results in broken debugging when
`FPU_SHARING` or `ARM_NONSECURE_PREEMPTIBLE_SECURE_CALLS`.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
GICR_TYPER is a 64 bit register. On AArch32 when one uses sys_read64(),
this results in ldrd instruction. When Zephyr runs as a VM, 'LDRD'
instruction on an emulated MMIO region gets trapped to the hypervisor as
data abort.
Refer the following paragraph from ARM DDI 0487G.b ID072021 :-
Section - "ISS encoding for an exception from a Data Abort",
"For other faults reported in ESR_EL2, ISV is 0 except for the following
stage 2 aborts:
AArch32 instructions where the instruction:
— Is an LDR, LDA, LDRT, LDRSH, LDRSHT, LDRH, LDAH, LDRHT, LDRSB, LDRSBT,
LDRB, LDAB, LDRBT, STR, STL, STRT, STRH, STLH, STRHT, STRB, STLB, or STRBT
instruction."
As 'LDRD' is not in the list, so ISV==0. This implies that Arm could not
decode the instruction for the hypervisor (in EL2) to execute it.
Thus, we have abstracted this read into arm_gic_get_typer().
For AArch64, we use sys_read64() as before.
For AArch32, we use sys_read32() twice to read the lower and upper 32 bits
of GICR_TYPER.
Thus, we ensure that when the access is trapped for AArch32, Arm generates
a valid ISS so that hypervisor can execute it.
Signed-off-by: Ayan Kumar Halder <ayankuma@amd.com>
The callback is now called whenever the PA sync is terminated,
even if it was locally terminated. The test case has been
updated to handle that.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
If using the advertiser list when syncing to a PA, then the
address address needs to be updated for the PA sync object.
This is a small optimization to avoid doing a copy when
the address and SID is already set.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
When deleting a PA sync with bt_le_per_adv_sync_delete
Zephyr should call the `term` callback for the PA sync
as per the documentation for the callback.
This was not done in the case that the PA sync was
terminated by local request.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
To avoid legacy extended adv repots blocking important
events or work, mark them as discaradble.
Signed-off-by: Martin Tverdal <martin.tverdal@nordicsemi.no>
Print the error messages about the state of the host register
when the I2C transfers fail. This is useful for debugging.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
DMIC does not need to use SOFT_RESET bit to start collecting data if
periodic_start bit is enabled.
Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
Move runtime checks to use arch_num_cpus() and build checks
to use CONFIG_MP_MAX_NUM_CPUS. This is to allow runtime
determination of the number of CPUs in the future.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
For test_1cpu_start/test_1cpu_stop make the code only build if
CONFIG_SMP and move to using arch_num_cpus() for runtime loops
and CONFIG_MP_MAX_NUM_CPUS for array decleration.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Move runtime checks to use arch_num_cpus() and build checks
to use CONFIG_MP_MAX_NUM_CPUS. This is to allow runtime
determination of the number of CPUs in the future.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Move runtime checks to use arch_num_cpus() and build checks
to use CONFIG_MP_MAX_NUM_CPUS. This is to allow runtime
determination of the number of CPUs in the future.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Move runtime checks to use arch_num_cpus() and build checks
to use CONFIG_MP_MAX_NUM_CPUS. This is to allow runtime
determination of the number of CPUs in the future.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Replace usage of CONFIG_MP_NUM_CPUS with CONFIG_MP_MAX_NUM_CPUS for
init and declaration as we phase out CONFIG_MP_NUM_CPUS usage.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
