LP/HP RING OSC clocks were replaced by the ACE IPLL clock.
If needed IPLL can be configured to work as low power clock. But right
now ACE uses only WOVCRO and IPLL (configured to work as HP RING OSC
clock).
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
LP/HP RING OSC clocks were replaced by the ACE IPLL clock.
If needed IPLL can be configured to work as low power clock. But right
now ACE uses only WOVCRO and IPLL (configured to work as HP RING OSC
clock).
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Selecting Low Power clock has the same result as selecting High
Performance clock (now IPLL). Therefore, the LP clock will be removed
from the list of available clocks on ACE family platforms.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
The ACE family platforms do not have LP/HP RING OSC clocks. They were
replaced by the ACE IP integrated PLL clock. Selecting LP or HP in
CLKCTL will result in enabling IPLL.
Clock can supply frequencies for both replaced clocks, default frequency
equals to 393.2 MHz.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
The ACE family platforms do not have LP/HP RING OSC clocks. They were
replaced by the ACE IP integrated PLL clock. Selecting LP or HP in
CLKCTL will result in enabling IPLL.
Clock can supply frequencies for both replaced clocks, default frequency
equals to 393.2 MHz.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Updating value of WOVRCO request bit in CLKCTL register according to the
documentation. Previus value was mask used for clock enabling.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This creates separate dtsi files for the various memory density codes of
SAM X2xfamilies (they are the same where the specific size exists.)
All of the boards with the exclusion of EV11L78A use the same density
model of 18 (32KiB RAM and 256KiB flash) which is what the samd2x.dtsi
include specified for all of them previously.
The density code has been confirmed being the same across the D20/D21,
C20/C21, L21, and R21 families. This does not carry over to some other
series such as the E5x.
Signed-off-by: Diego Elio Pettenò <flameeyes@meta.com>
The driver is bound to the module, there's no separate platform, so
let's just add the driver path to the module area so that changes for it
gets tagged and assigned.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
This internal kernel API is misplaced in a public kernel header. Just
make it available to the code using it in the kernel.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
If `pthread_exit()` is called from a `k_thread`, then we would
previously trigger an assertion. The problem with that, is that
is POSIX is acting as a compatibility layer.
Given that it is a reasonable expectation to have the calling
thread exit or abort when calling `pthread_exit()`, lets do just
that.
Signed-off-by: Christopher Friedt <cfriedt@meta.com>
New nrfx revision fixes issue in the PWM driver causing build
errors due to invalid include when workaround for anomaly 109
is enabled.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
The _EXPIRED macro is no longer necessary. It is a relic of an older
timeout processing algorithm from several years ago.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
NET_STATISTICS_PPP are dependend on NET_L2_PPP, not on NET_PPP.
This allows to use statistics also in modem subsys.
Signed-off-by: Wojciech Slenska <wsl@trackunit.com>
Add SRAM code region definition to RT6xx series SOC. The RT6xx shares
SRAM partitions between the code and data bus, but a default allocation
is chosen by the SOC level devicetree. The user can modify this
allocation by changing the base address and size of the sram_code and
sram0 regions in their board devicetree.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add SRAM code region definition to RT5xx series SOC. The RT5xx shares
SRAM partitions between the code and data bus, but a default allocation
is chosen by the SOC level devicetree. The user can modify this
allocation by changing the base address and size of the sram_code and
sram0 regions in their board devicetree.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The iMX RT bootrom allows the user to load images into RAM regions from
flash by providing a correctly configured boot header. In particular, if
the boot header contains a load address within RAM, the bootroom will
automatically copy the image to the load address before executing it
Introduce CONFIG_NXP_IMX_RT_ROM_RAMLOADER to enable this feature. This
Kconfig will shift the LMA of a image built to run in a RAM region to
reside in the default FlexSPI boot region, which allows the image to be
loaded to the FlexSPI region using west. This is intended to simplify
development of applications executing from RAM on iMX RT based systems.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add check for device busy when CONFIG_PM_NEED_ALL_DEVICES_IDLE is
set to y because one or more devices may still in busy and causes
problem when system go into low power in Intel ISH platform.
Signed-off-by: Leifu Zhao <leifu.zhao@intel.com>
If the users configures this option in devicetree, ie,
```
&uicr {
nfct-pins-as-gpios;
};
```
CMake will inject the HAL-specific CONFIG_NFCT_PINS_AS_GPIOS definition,
so that the necessary operations are performed during system init.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Usage of application level for device drivers needs to be avoided. Also
introduced a new init level, with default to 90 as other dependencies of
USB-C run at priority 80.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
In a first place, hardcoding priorities like this is a bad idea, but
this patch just moves the device to late POST_KERNEL stage, as
APPLICATION level should be avoided for device drivers.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
There's no need to use APPLICATION level. In case of the IPM console
test, priorities have been adjusted to make sure sender/receiver are
initialized in the correct order.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
There's no need to use APPLICATION level. Also create a custom init
level that runs late in the process (depends e.g. on SPI which runs at
high priority level, 70).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Convert the driver to a dt-based device. Also update Kconfig so that it
depends on the right compatible being enabled, initialize in POST_KERNEL
(APPLICATION should not be used for devices) and remove one redundant
include.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The device model was not used for anything useful, only to call some
init code. Change to SYS_INIT instead.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Rework the can_dlc_to_bytes table lookup code in a way that allow the
compiler to guess the resulting output and somehow fix the build
warning:
zephyr/drivers/can/can_nxp_s32_canxl.c:757:9: warning:
'__builtin___memcpy_chk' forming offset [16, 71] is out of the bounds
[0, 16] of object 'frame' with type 'struct can_frame' [-Warray-bounds]
757 | memcpy(frame->data, msg_data.data, can_dlc_to_bytes(frame->dlc));
where the compiler detects that frame->data is 8 bytes long but
can_dlc_to_bytes could return more than that.
Can be reproduced with:
west build -p -b s32z270dc2_rtu1_r52 \
-T samples/net/sockets/can/sample.net.sockets.can.one_socket
Suggested-by: Martin Jäger <martin@libre.solar>
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
This reverts commit 3127d7b54c which
was forgotten when switching back to breathe from docleaf and causing
unecessary "here's a warning about something that's not actually
a warning" :)
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Include the nrf peripheral kconfig definitions for all simulated
nrf boards, not just for the nrf52_bsim.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
