Add pinctrl-0 properties for configuration of UART, I2C, SPI, FTM,
DAC, ADC, ACMP, and PWT peripherals. These settings are based on what
is defined in the board/pinmux.c file.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add a function that uses the JESD216 SFDP BFP DW16 Enter 4-Byte
Addressing parameter to put the device into 4-byte addressing mode if
one of the entry modes that's supported by the driver is available on
the device.
Perform the transition if SFDP data is provided (either by devicetree
or at runtime), or if a special devicetree property provides the entry
mode descriptor.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Support both 24-bit and 32-bit address values when constructing the
device command. Note that some commands require 24-bit address
regardless of mode, and some require 32-bit addresses regardless of
mode, so provide command-specific overrides of a generic (but not yet
configurable) default address size.
With this we no longer need a special interface for READ_SFDP which
uses a 24-bit address but with a wait state introduced by clocking out
a fifth command byte.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
This driver abstracts most access through a generic function that
supports both read and write with and without address components in
the command. Rework this so that instead of distinct arguments
specifying the combination of features there's a flag set that will
allow more combinations to be specified.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Fixes#29915.
Implements the memory layout and MPU configuration for Ethernet buffers
for STM32H7 controllers as recommended by ST. 16 KB of SRAM3 are
are reserved for this. The first 256 B are for the RX/TX descriptors and
configured as strongly ordered, shareable memory. The rest is for RX/TX
buffers and configured as non cacheable memory. This configuration is
automatically applied for H7 chips if the SRAM3 memory is enabled in the
device tree.
Signed-off-by: Mario Jaun <mario.jaun@gmail.com>
When building and running the rpmsg_service sample on MPS2 AN521
use the mps2_an521_remote target to build the Zephyr image
for the remote core.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
When building and running the openamp sample on MPS2 AN521,
use the mps2_an521_remote target to build the Zephyr image
for the remote core.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
We do not need to have dependencies any more on !OPENAMP
for BUILD_WITH_TFM in the mps2 an521 target, because we
now have different targets for the non-secure version of
the board and the remote core.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Add a new target for MPS2 AN521, called mps2_an521_remote.
This target is used in dual image MPS2 AN521 builds, for
the 'remote' target. It is indentical to mps2_an521_nonsecure,
except for the fact that it does not enable TrustZone-M and
it does not set the security domain to Non-Secure.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Kconfig symbol is used in hal_stm32 module to define Cube HAL
symbol HSE_VALUE (cf hal_stm32/stm32cube/CMakeLists.txt).
Due to this specific usage, this symbol should be kept. As a
consequence it could not be replaced by dts equivalent but we can
use dts to configure it.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Optionally configure Kconfig SYS_CLOCK_HW_CYCLES_PER_SEC using
clock-frequency provided by dt if sysclk node is enabled
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Provided nodes reflect the clock tree of each series.
Clock nodes are disabled by default but populated with default
start up configuration. Main reason is the we don't want to
impact boards using Kconfig based clock configuration for now.
Exception to these rules:
- syslck: Default enabled, clock frequency and clock source not
provided
- pll: clock source not provided
This is made on purpose so that errors are triggered if parameters
essential to the board configuration are not provided.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
To allow transition to device tree based clock configuration on
stm32 targets, rework clock_control driver to use intermediate
STM32_ macros initially defined as the equivalent Kconfig macros
for now.
Propagate the change in all code using these macros.
The reason to introduce these new macros instead of configuring
Kconfig flags using dt kconfigfunctions is that we'll need
to be able to inform users that Kconfig flags are deprecated
once the whole family conversion is done, to encourage
out of tree users to adopt this new configuration scheme.
Note: For now STM32H7 series and code is excluded.
This is the same for some series specific code such as
PLL mul/div for L0/L1 and XTRE prescaler on F1 series.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The timestamp is no longer depending on TX/RX time config
options so move it to separate settings.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
This value is used to measure the RX/TX statistics. The previous
use of the timestamp field did not work in RX path as the timestamp
value could be overwritten by the driver if gPTP timestamping
is enabled. So to fix the RX statistics, use a separate field
for the create time.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
If user enables CONFIG_USERSPACE, then at least one TX or RX thread
is needed to isolate the application from the kernel space components.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
Set the default behaviour of the networking subsystem so that
no TX or RX threads are created. This will save RAM as there
is no need to allocate stack space for the RX/TX threads.
Also this will give small improvement to network packet latency
shown here:
* with 1 traffic class (1 TX and RX thread)
Avg TX net_pkt (42707) time 60 us [0->22->15->22=59 us]
Avg RX net_pkt (42697) time 36 us [0->10->3->12->7=32 us]
* with 0 traffic classes (no TX and RX threads)
Avg TX net_pkt (41608) time 42 us [0->21->20=41 us]
Avg RX net_pkt (41593) time 31 us [0->9->12->8=29 us]
In this qemu_x86 test run, 40k UDP packets was transferred between
echo-server and echo-client. In TX the speed increase was 30% and
in RX it was 14%.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
For testing purposes, add simulated PTP clock device to e1000
Ethernet driver that is used in qemu_x86 board. The PTP clock
does nothing useful as there is no real hw behind this device.
We just emulate the clock in order to do some SO_TXTIME testing.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
Set the net_pkt creation time just before the actual net_pkt
is allocated in order to get more accurate information for
statistics.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
It is possible that user wants to access PTP clock but does
not need gPTP support. The networking txtime sample does exactly
this.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
It is possible that user wants to access PTP clock but does
not need gPTP support. The networking txtime sample does exactly
this.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
If user has set the priority of the sent net_pkt to highest
priority (NET_PRIORITY_CA) and enabled CONFIG_NET_TC_SKIP_FOR_HIGH_PRIO
option, then push that packet directly to driver instead of TX queue.
This will make the TX sending latency smaller for the high priority
packet. This is not enabled by default.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
This application shows how to use SO_TXTIME option, which can be
used to specify the time when the network packet should be sent
out by the network device driver.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
Tests are designed to run over the DUMMY interface but when run on
hardware, net_if_get_default() can return the actual hardware
interface.
Fixes: #31969
Signed-off-by: David Leach <david.leach@nxp.com>
If there is a UARTE receive error (e.g. framing or break), the RXTO
event may never come. Check error event too, to avoid an infinite loop.
Signed-off-by: Jim Paris <jim@jim.sh>
This CL adds a override mechanism for pwm module's input clock source
assignment. If the 'clock-bus' property exists, the NPCX_DT_PROP_ENUM_OR
macro function will return an enum upper token value. Otherwise, it
expands to default value in 'clocks' property.
For example, if the users want to select LFCLK as pwm0's input clock,
ths node can be overridden by adding 'clock-bus' property with an enum
string, "NPCX_CLOCK_BUS_LFCLK".
&pwm0 {
status = "okay";
clock-bus = "NPCX_CLOCK_BUS_LFCLK";
};
Signed-off-by: Keith Short <keithshort@google.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
It's easier and safer to parse json file rather than extract
total size from stdout
Now the .json file has two keys:
{
"symbols": {
"children": [
...
],
"identifier": ":",
"name": "root",
"size": 2220
},
"total_size": 34272
}
Signed-off-by: Jingru Wang <jingru@synopsys.com>
i2s1 is not present in all stm32f4 series. So moving the i2s1 node
from the top level stm32f4 dtsi file to the stm32fxx specific dtsi
files. Also in stm32f429zi, the sequence starts from i2s2, this commit
helps in having the right channel number.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
Replace all existing deprecated API with the recommended alternative.
Fixes#34102
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Add dts nodes for onboard devices that have drivers in zerphyr src
- Add PWM for all leds
- Add LSM303AGR sensor node
- Add LSM303DLHC node for PCB rev B
- Create PCB rev B overlay and make PCB rev D default.
Signed-off-by: Sahaj Sarup <sahaj.sarup@linaro.org>
After the introduction of usart1 the kernel/genisr_table test could
no longer build, due to an interrupt conflict.
Adopt the TEST_NUM_IRQS to resolve the conflict.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Adds nucleo_g071rb board to the uart_async_api test.
Therefore additionally add usart1 in board definitions.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Fix stm32_dma_is_irq_active not checking the IRQ status(IsEnabled) for
active interrupts.
While the transfer-complete, half-transfer comp. and transfer-error
is_XX_irq_active() functions check for IRQ status (IsEnabled),
ORing the result with dma_stm32_is_gi_active() overrides the
status check as gi is always 1 in case any of these flags is active.
Related to commit 96c92ed93f.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Enables dma test cases loop_transfer and chan_blen_transfer
on stm32g03116_disco, nucleo_g071rb and nucleo_g0b1re.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Use LL_DMAMUX_CHANNEL_x defines instead of DMAMUX_CSR_SOF7x to check
if corresponding LL_DMAMUX_IsActiveFlag_SOx and LL_DMAMUX_ClearFlag_SOx
inline functions exist and should be added to func_ll_is_active_so[]
and func_ll_clear_so[].
The HAL of some socs uses the same flag to decide which registers exist
on a specific soc. And the same defines are used for table_ll_channel[]
initializations.
This is necessary because DMAMUX_CSR_SOF5 and DMAMUX_CSR_SOF6 were
wrongly added in the HALs soc header file for some stm32g0 socs,
therefore without this change some stm32g0 socs couldn't compile.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Update the existing driver to support STM32G0 series.
It enables the DMA_STM32_SHARED_IRQS flag for g0 series, such that
all interrupts are handled in a shared isr to avoid irq conflicts.
The shared isr is extended to be able to handle irqs from more than one
dma instance.
Furthermore the config_irq function of instance 1, which connects to the
irqs, was reworked to avoid irq conflicts when 2 dma instances on
stm32f0, or stm32g0 are enabled:
While dma1 has one exclusive irq for channel 1, and one irq for dma1
channels 2 and 3, all other channels share the same irq.
Therefore it is currently not possible to enable dma2 without enabling
dma1 at the same time, without getting an build errror due to an irq
conflict.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
