-Add DMA channel details for the SPI DMA transfer
-Reserve HEAP_SPACE for DMA channel descriptors
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
1, Change the allocation of DMA descriptors for the case
when multiple buffers are used for DMA transfer. This was
tested during SPI DMA transfers
2. Add support for the case when source and destination
addresses should not be incremented.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
The DMA channel number used for the DMA transfer can now
be specified from the device tree config files
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Fix race condition in build when creating libraries in application and
depending on zephyr_interface.
lib/CMakeLists.txt:
add_library(lib STATIC src/lib.c)
zephyr_append_cmake_library(lib)
target_link_libraries(lib PUBLIC zephyr_interface)
Gives following error message:
from path/src/lib.c:6:
zephyr/include/syscall.h:11:10: fatal error: syscall_list.h: \
No such file or directory
11 | #include <syscall_list.h>
| ^~~~~~~~~~~~~~~~
compilation terminated.
[13/165] Generating include/generated/syscall_dispatch.c, \
include/generated/syscall_list.h
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Remove generated files from DEPENDS list of custom commands.
The custom target PARSE_SYSCALLS_TARGET exist for these targets and
is already on the DEPENDS list.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
There is a warning because of some pointer arithmetics in Grub,
that makes the build fail. The build works after disabling -Werror.
Signed-off-by: Maximilian Bachmann <m.bachmann@acontis.com>
Fix incorrect return value check when converting pinctrl
format to existing pin config format
Signed-off-by: Marin Jurjevic <marin.jurjevic@hotmail.com>
Use conversion macros to convert Extended Scan duration and
period to radio event counts.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
Added implementation to support simultaneous 1M and Coded
PHY Extended Scanning duration and period. Also, added
implementation to support update to duration and period of
an active scanning instance.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
Fix the ll_scan_enable interface signature, place duration
before period parameter to reflect the order as in the HCI
LE Set Extended Scan Enable command.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
Fix scan done to be generated when the window is closed
both under abort and graceful window close.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
Move the implementation to set scanning channel to
isr_window function where the next window is started,
instead of being at the abort of the previous continuous
window.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
Fix scanning state and is_adv_ind flags to be common to both
isr_done and isr_window code path.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
Refactoring of conditional compilation related to extended
scanning with duration and period.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
Rework implementation handling the disable and the error
handling when failure to start Periodic Advertising
instance.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
Fix incorrect use of unint32_t instead of a sufficient
uint8_t for the returned HCI error code.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
Decouple updates to primary and secondary AD Data PDU such
that primary PDU changes can be committed on successful
scheduling of secondary PDU radio events.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
Do not create bin file and remove all clutter. In this case we are
generating 1GB of data that will not be used.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The linker will emit a warning condition when a section with a
declared alignment doesn't naturally start on that alignment (which
begets the question of why the declared alignment syntax exists at
all...).
Do the alignment for .bss between the sections instead as a simple
workaround.
Note that this alignment isn't architecturally required, as current
Zephyr targets don't use the page-aligned pseudo-MMU on this hardware;
the only requirement is alignment to the 64 byte cache stride. It
should work to pack .bss tightly. But when I try that, I get an error
from the rimage tool, which is apparently unprepared for
non-4k-aligned sections?
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The header scheme for the IPM_CAVS_IDC driver changed and this legacy
platform (which is really a very close cousin of intel_adsp/cavs_v15)
broke. Fix things up. Longer term we should unify the two.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
There are now two timer drivers available for various xtensa
platforms. Select based on their driver and not the architecture.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Add a printk default hook that works in very early boot and doesn't
depend on the logging subsystem (which can still be used if desired,
of course). It speaks the same protocol, is somewhat smaller (MUCH
smaller if the app doesn't otherwise need the logging and ring buffer
dependencies), and more efficiently uses the output slot space by
doing line buffering and flushing only when needed.
Most importantly this one is MP-safe via both locking and cache
coherence management, and can work reliably when SMP is enabled.
(Note that "reliable" means that all output appears without corruption
-- simulateous logging by two CPUs can still interleave bytes, of
course).
Longer term, if we keep this protocol it would be good to unify the
two backends to reduce duplicated code.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Implement the kernel "coherence" API on top of the linker
cached/uncached mapping work.
Add Xtensa handling for the stack coherence API.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Xtensa CPUs have incoherent L1 caches, which is deeply inconvenient
for SMP systems. But as a treatment for this, the ADSP memory map
contains the RAM twice, in separate 512MB regions that can be managed
separately by the Xtensa TLB/cacheattr mechanism. The low mapping is
set to bypass the cache where the high mapping is cached.
Set up linkage to use both as appropriate, then reassemble the final
sections to a contiguous region. Read-only areas (.text, .rodata) are
cached. Data sections are uncached by default, except for a special
".cache" section that may be used by higher level code to flag static
areas (e.g. stacks) which don't store multiprocessor-shared content.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The SoC definitions have the necessary IPC/IDC bits so there is
no need to define them separately.
Originally-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
