ipm: cavs_idc: use the IPC/IDC definitions in SoC
The SoC definitions have the necessary IPC/IDC bits so there is no need to define them separately. Originally-by: Daniel Leung <daniel.leung@intel.com> Signed-off-by: Daniel Leung <daniel.leung@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
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4 changed files with 31 additions and 65 deletions
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@ -101,7 +101,8 @@ config IPM_STM32_IPCC_PROCID
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config IPM_CAVS_IDC
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bool "CAVS DSP Intra-DSP Communication (IDC) driver"
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depends on SMP && CAVS_ICTL
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depends on IPM && CAVS_ICTL
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default y if MP_NUM_CPUS > 1 && SMP
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help
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Driver for the Intra-DSP Communication (IDC) channel for
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cross SoC communications.
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@ -13,9 +13,10 @@
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#include <arch/common/sys_io.h>
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#include <soc.h>
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#include <soc/shim.h>
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#include <adsp/io.h>
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#include "ipm_cavs_idc.h"
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#include "ipm_cavs_idc_priv.h"
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#ifdef CONFIG_SCHED_IPI_SUPPORTED
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extern void z_sched_ipi(void);
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@ -47,15 +48,15 @@ static void cavs_idc_isr(const struct device *dev)
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continue;
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}
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idctfc = idc_read(REG_IDCTFC(i), curr_cpu_id);
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idctfc = idc_read(IPC_IDCTFC(i), curr_cpu_id);
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if ((idctfc & REG_IDCTFC_BUSY) == 0) {
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if ((idctfc & IPC_IDCTFC_BUSY) == 0) {
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/* No message from this core */
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continue;
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}
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/* Extract the message */
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id = idctfc & REG_IDCTFC_MSG_MASK;
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id = idctfc & IPC_IDCTFC_MSG_MASK;
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switch (id) {
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#ifdef CONFIG_SCHED_IPI_SUPPORTED
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@ -66,16 +67,16 @@ static void cavs_idc_isr(const struct device *dev)
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default:
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if (drv_data->cb != NULL) {
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ext = UINT_TO_POINTER(
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idc_read(REG_IDCTEFC(i), curr_cpu_id) &
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REG_IDCTEFC_MSG_MASK);
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drv_data->cb(dev, drv_data->user_data, id, ext);
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idc_read(IPC_IDCTEFC(i), curr_cpu_id) &
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IPC_IDCTEFC_MSG_MASK);
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drv_data->cb(dev, drv_data->user_data, id, ext);
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}
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break;
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}
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/* Reset busy bit by writing to it */
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idctfc |= REG_IDCTFC_BUSY;
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idc_write(REG_IDCTFC(i), curr_cpu_id, idctfc);
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idctfc |= IPC_IDCTFC_BUSY;
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idc_write(IPC_IDCTFC(i), curr_cpu_id, idctfc);
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}
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#ifdef CONFIG_SCHED_IPI_SUPPORTED
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if (do_sched_ipi) {
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@ -105,8 +106,8 @@ static int cavs_idc_send(const struct device *dev, int wait, uint32_t id,
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continue;
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}
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reg = idc_read(REG_IDCITC(i), curr_cpu_id);
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if ((reg & REG_IDCITC_BUSY) != 0) {
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reg = idc_read(IPC_IDCITC(i), curr_cpu_id);
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if ((reg & IPC_IDCITC_BUSY) != 0) {
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busy = true;
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break;
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}
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@ -117,9 +118,9 @@ static int cavs_idc_send(const struct device *dev, int wait, uint32_t id,
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return -EBUSY;
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}
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id &= REG_IDCITC_MSG_MASK;
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ext &= REG_IDCIETC_MSG_MASK;
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ext |= REG_IDCIETC_DONE; /* always clear DONE bit */
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id &= IPC_IDCITC_MSG_MASK;
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ext &= IPC_IDCIETC_MSG_MASK;
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ext |= IPC_IDCIETC_DONE; /* always clear DONE bit */
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for (i = 0; i < CONFIG_MP_NUM_CPUS; i++) {
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if (i == curr_cpu_id) {
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@ -127,8 +128,8 @@ static int cavs_idc_send(const struct device *dev, int wait, uint32_t id,
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continue;
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}
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idc_write(REG_IDCIETC(i), curr_cpu_id, ext);
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idc_write(REG_IDCITC(i), curr_cpu_id, id | REG_IDCITC_BUSY);
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idc_write(IPC_IDCIETC(i), curr_cpu_id, ext);
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idc_write(IPC_IDCITC(i), curr_cpu_id, id | IPC_IDCITC_BUSY);
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}
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return 0;
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@ -187,11 +188,11 @@ static int cavs_idc_set_enabled(const struct device *dev, int enable)
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continue;
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}
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mask |= REG_IDCCTL_IDCTBIE(j);
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mask |= IPC_IDCCTL_IDCTBIE(j);
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}
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}
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idc_write(REG_IDCCTL, i, mask);
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idc_write(IPC_IDCCTL, i, mask);
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/* FIXME: when we have API to enable IRQ on specific core. */
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sys_set_bit(DT_REG_ADDR(DT_NODELABEL(cavs0)) + 0x04 +
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@ -33,4 +33,14 @@
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#define IPM_CAVS_IDC_MSG_SCHED_IPI_ID \
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(CAVS_IDC_TYPE(0x7FU) | CAVS_IDC_HEADER(0x495049U))
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static inline uint32_t idc_read(uint32_t reg, uint32_t core_id)
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{
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return *((volatile uint32_t*)(IPC_DSP_BASE(core_id) + reg));
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}
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static inline void idc_write(uint32_t reg, uint32_t core_id, uint32_t val)
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{
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*((volatile uint32_t*)(IPC_DSP_BASE(core_id) + reg)) = val;
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}
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#endif /* ZEPHYR_DRIVERS_IPM_IPM_CAVS_IDC_H_ */
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@ -1,46 +0,0 @@
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/*
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* Copyright (c) 2020 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_IPM_IPM_CAVS_IDC_PRIV_H_
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#define ZEPHYR_DRIVERS_IPM_IPM_CAVS_IDC_PRIV_H_
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#define IDC_REG_SIZE DT_REG_SIZE(DT_INST(0, intel_cavs_idc))
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#define IDC_REG_BASE(x) \
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(DT_REG_ADDR(DT_INST(0, intel_cavs_idc)) + x * IDC_REG_SIZE)
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#define IDC_CPU_OFFSET 0x10
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#define REG_IDCTFC(x) (0x0 + x * IDC_CPU_OFFSET)
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#define REG_IDCTEFC(x) (0x4 + x * IDC_CPU_OFFSET)
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#define REG_IDCITC(x) (0x8 + x * IDC_CPU_OFFSET)
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#define REG_IDCIETC(x) (0xc + x * IDC_CPU_OFFSET)
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#define REG_IDCCTL 0x50
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#define REG_IDCTFC_BUSY (1 << 31)
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#define REG_IDCTFC_MSG_MASK 0x7FFFFFFF
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#define REG_IDCTEFC_MSG_MASK 0x3FFFFFFF
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#define REG_IDCITC_BUSY (1 << 31)
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#define REG_IDCITC_MSG_MASK 0x7FFFFFFF
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#define REG_IDCIETC_DONE (1 << 30)
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#define REG_IDCIETC_MSG_MASK 0x3FFFFFFF
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#define REG_IDCCTL_IDCIDIE(x) (0x100 << (x))
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#define REG_IDCCTL_IDCTBIE(x) (0x1 << (x))
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static inline uint32_t idc_read(uint32_t reg, uint32_t core_id)
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{
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return sys_read32(IDC_REG_BASE(core_id) + reg);
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}
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static inline void idc_write(uint32_t reg, uint32_t core_id, uint32_t val)
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{
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sys_write32(val, IDC_REG_BASE(core_id) + reg);
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}
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#endif /* ZEPHYR_DRIVERS_IPM_IPM_CAVS_IDC_PRIV_H_ */
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