4 commits

Author	SHA1	Message	Date
Mohamed ElShahawi	f9e0fa9af3	drivers: esp32/clock_control: support UART, I2C ... - Change default CPU Clock to 240MHz (PLL is activated) - I2C, UART will use sysclk from clock driver - esp32_enable_peripheral replaced by clock_control_on Signed-off-by: Mohamed ElShahawi <ExtremeGTX@hotmail.com>	2020-06-16 09:00:51 -05:00
Mohamed ElShahawi	4acac3e9ef	drivers: esp32/clock_control: Add Clock Driver ... - Support PLL for Higher Frequencies 80,160,240 MHz - Support XTAL Frequencies 26MHz, 40MHz - Clock Driver can't be disabled, because all of the other drivers will depend on it to get their operating Frequency based on chosen clock source (XTAL/PLL). - Add needed references to BBPLL i2c bus ROM functions. - Add `rtc` node to Device Tree. - Since All Peripherals Frequency is depending on CPU_CLK Source, `clock-source` property added to CPU node Signed-off-by: Mohamed ElShahawi <ExtremeGTX@hotmail.com>	2020-06-16 09:00:51 -05:00
Kumar Gala	a1b77fd589	zephyr: replace zephyr integer types with C99 types ... git grep -l 'u\(8\|16\|32\|64\)_t' | \ xargs sed -i "s/u\(8\|16\|32\|64\)_t/uint\1_t/g" git grep -l 's\(8\|16\|32\|64\)_t' | \ xargs sed -i "s/s\(8\|16\|32\|64\)_t/int\1_t/g" Signed-off-by: Kumar Gala <kumar.gala@linaro.org>	2020-06-08 08:23:57 -05:00
Anas Nashif	cea0b3a9c2	xtensa: move soc to top-level dir soc/ ... Move the SoC outside of the architecture tree and put them at the same level as boards and architectures allowing both SoCs and boards to be maintained outside the tree. Signed-off-by: Anas Nashif <anas.nashif@intel.com>	2018-09-13 00:56:48 -04:00

Renamed from arch/xtensa/soc/esp32/soc.h (Browse further)