4acac3e9ef
- Support PLL for Higher Frequencies 80,160,240 MHz - Support XTAL Frequencies 26MHz, 40MHz - Clock Driver can't be disabled, because all of the other drivers will depend on it to get their operating Frequency based on chosen clock source (XTAL/PLL). - Add needed references to BBPLL i2c bus ROM functions. - Add `rtc` node to Device Tree. - Since All Peripherals Frequency is depending on CPU_CLK Source, `clock-source` property added to CPU node Signed-off-by: Mohamed ElShahawi <ExtremeGTX@hotmail.com>
67 lines
1.9 KiB
C
67 lines
1.9 KiB
C
/*
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* Copyright (c) 2017 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __SOC_H__
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#define __SOC_H__
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#include <soc/dport_reg.h>
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#include <soc/rtc_cntl_reg.h>
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#include <rom/ets_sys.h>
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#include <zephyr/types.h>
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#include <stdbool.h>
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#include <arch/xtensa/arch.h>
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/**
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* @brief Struct to peripheral masks to enable peripheral
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* clock and reset peripherals.
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*/
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struct esp32_peripheral {
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/** Mask for clock peripheral */
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int clk;
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/** Mask for reset peripheral */
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int rst;
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};
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static inline void esp32_set_mask32(uint32_t v, uint32_t mem_addr)
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{
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sys_write32(sys_read32(mem_addr) | v, mem_addr);
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}
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static inline void esp32_clear_mask32(uint32_t v, uint32_t mem_addr)
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{
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sys_write32(sys_read32(mem_addr) & ~v, mem_addr);
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}
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static inline void esp32_enable_peripheral(const struct esp32_peripheral *peripheral)
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{
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esp32_set_mask32(peripheral->clk, DPORT_PERIP_CLK_EN_REG);
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esp32_clear_mask32(peripheral->rst, DPORT_PERIP_RST_EN_REG);
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}
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extern int esp32_rom_intr_matrix_set(int cpu_no,
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int interrupt_src,
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int interrupt_line);
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extern int esp32_rom_gpio_matrix_in(uint32_t gpio, uint32_t signal_index,
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bool inverted);
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extern int esp32_rom_gpio_matrix_out(uint32_t gpio, uint32_t signal_index,
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bool out_inverted,
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bool out_enabled_inverted);
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extern void esp32_rom_uart_attach(void);
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extern void esp32_rom_uart_tx_wait_idle(uint8_t uart_no);
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extern STATUS esp32_rom_uart_tx_one_char(uint8_t chr);
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extern STATUS esp32_rom_uart_rx_one_char(uint8_t *chr);
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extern void esp32_rom_Cache_Flush(int cpu);
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extern void esp32_rom_Cache_Read_Enable(int cpu);
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extern void esp32_rom_ets_set_appcpu_boot_addr(void *addr);
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/* ROM functions which read/write internal i2c control bus for PLL, APLL */
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extern uint8_t esp32_rom_i2c_readReg(uint8_t block, uint8_t host_id, uint8_t reg_add);
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extern void esp32_rom_i2c_writeReg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data);
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#endif /* __SOC_H__ */
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