The SoC selections for each architecture are moved to the top level
in menuconfig and xconfig. This makes it more intuitive to select
architecture -> SoC -> then board, avoiding an additional trip to
go into the architecture menu to select SoC.
Change-Id: I57a78a09adfc4bb12423915b6ad14ceb74381a2b
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The nmi_on_reset.S functions are used by all ARM platforms. It
makes no sense to repeat the same code for all platforms. Moving
the code from each SOC implementation to arch/arm/core.
The same treatment for the NMI_INIT() macro. Moving it from a per
SOC implementation to the include/arch/arm/cortex_m/nmi.h.
Change-Id: I574d8880a44046cc7b9e1b635e80d6e83657b8c1
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
The thread monitor allows to iterate over the thread context
structures for each existing thread (fiber/task) in the system.
Thread context structures do not expose thread entry information
directly. Although all the information can be scavenged from memory
stacks. Besides, accessing the information depends on the stack
implementation for each architecture.
By extending the tcs we allow a direct access to the thread
entry point and its parameters, only when thread monitor is
enabled.
It also allows a task to access its kernel task structure
through the first parameter of the thread.
This allows a debugger application to access the information directly
from the thread context structures list.
Change-Id: I0a435942b80eddffdf405016ac4056eb7aa1239c
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@intel.com>
This reverts commit 3f6884902b.
This commit does not work as intended: the part in arch/arm/Makefile
gets ignored and -mcpu=cortex-m3/4 does not get passed to gcc. It seems
that the zephyr toolchain does not care, but the vxworks assembler
chokes if it is missing, and thinks the CPU does not support thumb ISA
Change-Id: I14d11d3e22dac4952bdab3eb9e2d1c36b1a686c2
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Support for Freescale/NXP K64 SPI modules, limited to:
- Master mode
- A single active set of clock and transfer attributes (CTAR0), which
includes non-adjustable delay parameters
- Tx FIFO fill and Rx FIFO drain interrupt handling
- Standard, continuous select and continuous SCK SPI transfer formats
Also, divide-by-zero code generation in this driver is prevented.
The 'volatile' attribute is added to some of the variables in the baud
rate and delay calculation functions of the K64 SPI driver in order to
prevent bad code generation by gcc toolchains for ARM seen when an
optimization setting above -O0 is used.
Specifically, a register is loaded with the constant 0 and is used as
the divisor in a following divide instruction, resulting in a
divide-by-zero exception.
This issue has been seen with gcc versions 4.8.1 (the VxWorks toolchain)
and 5.2.0 (the Zephyr SDK toolchain).
Change-Id: Ib5b2b748aad8fdfd5e8d40544e6e1abef3713abe
Signed-off-by: Jeff Blais <jeff.blais@windriver.com>
Internal K64 SoC clock dividers were hard-coded. They've been replaced
with config options.
Change-Id: I583307f2e3341525f4445e9ceb89d36634b12802
Signed-off-by: Jeff Blais <jeff.blais@windriver.com>
PWM support using the Freescale K64 FlexTimer Module (FTM)
Change-Id: Iaad429c01bd877babba04e84d6a4679bd7e38120
Work-by: Mike Hirst <michael.hirst@windriver.com>
Signed-off-by: Jeff Blais <jeff.blais@windriver.com>
K64 pinmux support is created as a normal driver.
As opposed to the Galileo board, the pin configuration options are
defined by the MCU and are not board-specific. Separate
platform/board-specific configuration code uses the pinmux driver for
the default pin settings. For FRDM-K64F, only the Arduino pins (22 of a
possible 160) are set up.
Some of the I/O pins routed to the Arduino header are also configured as
JTAG/SWD signals by default and are used by the OpenSDAv2 debug
interface. Therefore, a PRESERVE_JTAG_IO_PINS config option was created
for the FRDM-K64 platform to prevent the default pin settings from
re-configuring these pins.
The K64 MCU separates pin configuration and control, implemented in the
pinmux driver, from GPIO. This results in some cross referencing
between the K64 GPIO driver and the K64 pinmux driver due to the
dependencies of one on the other.
This pinmux driver also uses the expanded pinmux function/mode parameter
size to describe pin configuration options with bit fields for the K64,
including up to 8 pin functions, plus interrupt, pullup/down, drive
strength, open-drain and slew rate.
The following GCC warnings in the K64 pinmux driver are prevented when not
compiling with 'no-optimization' (-O0):
warning: 'gpio_dev' may be used uninitialized in this function
[-Wmaybe-uninitialized]
Change-Id: Ie5031d18750143bf895883058b3cd55fd9989fd3
Signed-off-by: Jeff Blais <jeff.blais@windriver.com>
Basic driver support for the Freescale K64 GPIO module.
Note that only pin direction, read and write are supported.
Change-Id: I6587bb260197a00497be9ac991002e3dde54718d
Signed-off-by: Jeff Blais <jeff.blais@windriver.com>
This table was still being added to ROM even if
CONFIG_SW_ISR_TABLE=n.
Change-Id: Ia0de1349960af1c62e88344b3d5b6655b638219b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This config option is no longer implemented and doesn't actually
do anything.
Change-Id: I57ab7ba688f57da21f8a58f62ea37dc6b8daaf18
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We don't support hard-coding vectors in this table anymore.
If someone really wants to do this, they can set
IRQ_VECTOR_TABLE_CUSTOM and define their own.
Change-Id: I45f49782ba5fefb0a02eab02ec96efd0019bc6d5
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The peripherals utilizing UART were required to register their own
ISR rountines. This means that all those peripherals drivers need
to know which IRQ line is attached to a UART controller, and all
the other config values required to register a ISR. This causes
scalibility issue as every board and peripherals have to define
those values.
Another reason for this patch is to support virtual serial ports.
Virtual serial ports do not have physical interrupt lines to
attach, and thus would not work.
This patch adds a simple callback mechanism, which calls a function
when UART interrupts are triggered. The low level plumbing still needs
to be done by the peripheral drivers, as these drivers may need to
access low level capability of UART to function correctly. This simply
moves the interrupt setup into the UART drivers themselves. By doing
this, the peripheral drivers do not need to know all the config values
to properly setup the interrupts and attaching the ISR. One drawback
is that this adds to the interrupt latency.
Note that this patch breaks backward compatibility in terms of
setting up interrupt for UART controller. How to use UART is still
the same.
This also addresses the following issues:
() UART driver for Atmel SAM3 currently does not support interrupts.
So remove the code from vector table. This will be updated when
there is interrupt support for the driver.
() Corrected some config options for Stellaris UART driver.
This was tested with samples/shell on Arduino 101, and on QEMU
(Cortex-M3 and x86).
Origin: original code
Change-Id: Ib4593d8ccd711f4e97d388c7293205d213be1aec
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Currently the build system has hardcoded values for the -march/-mcpu
which identify what architecture should be used when compiling ARM code.
For processors such as the STM32 this will need to be defined by a per
SOC process.
Change-Id: Ia8158cd687d8d0432ea420e204bb2bc67d33a054
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
This patch updates some help sections to remove the "ERROR:
Unexpected indentation" messages during hmtl documentation
generation.
Change-Id: Idcdc17727b921b6145f9eb28d85975ceca273ce2
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
The app-facing interface for configuring interrupts was never
formally defined, instead it was defined separately for each arch
in their respective arch-specific header files. Occasionally these
would go out of sync.
Now there is a single irq.h header which defines this interface.
To avoid runtime overhead, these map to _arch_* implementations of
each that must be defined in headers pulled in by arch/cpu.h.
Change-Id: I69afbeff31fd07f981b5b291f3c427296b00a4ef
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We have a new policy: users should not be able to configure
an interrupt with "forbidden" priority levels, and any priority
levels with special semantics will be activated by flags.
Change-Id: I757c19cfedcb1d0938eaf4da348ddafb71b3e001
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Adds the driver to utilize the I2C/TWI interface on Atmel SAM3
family processors for I2C communication.
Note that this currently only supports master mode. Limited
testing has been done using the Fujitsu FRAM sample app.
Change-Id: Ibdb8277e47dd9450b49a66a95421eb1ffb1c4eb4
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Adds the struct to describe PDC (Peripheral DMA Controller).
The PDC is being used by peripherals to initiate DMA
transfers.
Change-Id: Ida2a20810c4f2ef972e9669c45e22da07c1576ab
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Decisions on compiler optimizations were done on the architecture level,
this does not scale and some SoCs will have different optimization levels
or compiler options needed. Moving this to the SoC makes it easy to optimize
differently when using the same CPU which we use to set the right optimization
now on the architecture level.
For IAMCU platforms, use the right architecture and tuning.
-march=lakemont -mtune=lakemont -miamcu -msoft-float
Change-Id: I458afca5feb9be5de8dcae559d6dcac3c6d6a2a7
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The default Kconfig option is missing a condition for the SRAM
base address on SAM3X8E. Add it back so the correct default
can be used.
Change-Id: Ib4103366f693648c76630cbbd71ca98109381d5c
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The PIO controllers on Atmel SAM3 family processors can be
used for GPIOs, so this is the driver.
Change-Id: I3d5712f3a0a71025b820ca1c08dd767ee1e136d8
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Mostly SoC initialization and some kernel subsystems, but also some
device drivers like the interrupt controllers.
Change-Id: I8dc1844c33acd877c075b6b03558fdca6f87500b
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
This is the last step before obsoleting DEVICE_DEFINE() and
DEVICE_INIT_CONFIG_DEFINE().
Change-Id: Ica4257662969048083ab9839872b4b437b8b351b
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Rename it to DEVICE_DEFINE() so that it fits in the 'device' namespace.
Change-Id: I3af3a39cf9154359b31d22729d0db9f710cd202b
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Rename it to DEVICE_INIT_CONFIG_DEFINE(), because (a) it was not fitting
in any namespace and (b) it is not used to declare, but rather define a
object.
Change-Id: I1da5822f06b85a9fb024b5b184afd0ccc01012ec
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Static interrupts rely on a trick where the _sw_isr_table array
is declared with each element in a different .gnu.linkonce
section, initially pointing to the spurious IRQ handler.
When drivers or apps declare their own interrupts, they override
the element with their own containing the real ISR and parameter.
However, this only works if the initial declaration of the
_sw_isr_table array with the spurious handlers is linked last.
App-specific code was being linked later than the core code,
causing static interrupts declared in apps not to be installed
correctly.
If the _sw_isr_table is moved from SOC-specific code to core arch
code, interrupts configured under soc/ should still also work.
Change-Id: Iec7df47386dfbbf2956a807da27dc8aa6e01b268
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This simulates a reboot by jumping back to the address stored in the
reset vector in vector table found at address 0. It is supported from
interrupt/exception level, which means that sys_arch_reboot() in this
case finds out if it is called from thread mode or handler mode, and in
the latter case, it unwinds the nested exception stack as needed.
Change-Id: Ib67f850f8411f1ee8fc592a5f31f2f70d0af14a4
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
The bootloader expects the entry point to be called __start, not __reset.
Change-Id: I5a5f7f45c248b9398e58fb026c731f8617fe4856
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Add sys_exc_connect() (and its x86-compatible alias nanoCpuExcConnect())
that allows connecting an exception handler at runtime.
The current implementation is a bit of a bastard, to avoid disturbing
the current implementation of the exception handlers. Instead of hooking
_exc_wrapper() in all vectors and adapting the exception handlers, the
current exception handlers are still hooked directly in the vectors.
When an exception is hooked at runtime, _exc_wrapper() gets installed in
the vector and the real handler gets inserted in _sw_exc_table; this
means that the scheme only works with non-XIP kernels.
This should be enhanced so that _exc_wrapper() is hooked in all vectors,
and that current exception handlers (for faults mostly) are reworked to
be inserted in the _sw_exc_table and wrapped in _exc_wrapper().
Change-Id: Icaa14f4835b57873d2905b7fbcbb94eeb3b247d1
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
For non-XIP systems, it's not in ROM, so remove the "ROM" part. Adapt it
to coding conventions at the same time, and export it to C code.
Change-Id: Id09a6be8bc9c462667ed71b53be7fa5382c88db3
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Find out on which stack the stack frame for an exception is in the assembly
code (__fault()) rather than in C (_Fault()). This will allow pushing
more registers on the stack when debugging is enabled.
Change-Id: I1c510b83098536f8930392b17df27511ccd04d80
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Rename the function and allow it to handle the 'type'
argument, which is ignored in this case.
Change-Id: I3d3493bea4511b2d026747505e7e52c5acc85012
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
The ESF was built using the 'alias' names of the GPRs (a1, lr, pc, etc)
rather than their 'real' name (rN).
Change-Id: I49cae5e94869a79a3165dc7f2347d8cec39dbf67
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
The processor is made aware that the vector table built in the image is
located at the start of SRAM in the case of a non-XIP image, rather than
at 0 in as is the case in XIP images.
Change-Id: I40b28ca32daf3e8930f103224766ed4e0ccc88e0
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
The image will be linked at a different address and with different
ROM/RAM sizes to allow running a bootloder image that loads a payload
image. The addresses/sizes depend on if it is a XIP image or not
(CONFIG_XIP), and in the case of a XIP image, if it is a bootloader
image (CONFIG_IS_BOOTLOADER) or not.
In the case of a bootloader, it is given the full ROM and
CONFIG_BOOTLOADER_SRAM_SIZE kB of SRAM. When not a XIP image, it is given
the full SRAM minus CONFIG_BOOTLOADER_SRAM_SIZE kB, and is linked at the
start of SRAM.
Change-Id: Ibbb693c7bff022f313dac40f21c04a61f4bed115
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
This board needs 16 bytes to be written with a specific value when the
target boots. This is only necessary when running a XIP image which
exists around those 16 bytes.
Change-Id: Ifd26b3842f09137765d9c7d1678476bfda8a563f
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Signed-off-by: Vlad Lungu <vlad.lungu@windriver.com>
Fix an issue where, if a task is pending on a nano timeout, the duration
it wants to wait is not taken into account by the tickless idle code.
This could cause a system to wait forever, or to the limit of the timer
hardware (which is forever, for all intents and purposes).
This fix is to add one field in the nanokernel data structure for one
task to record the amount of ticks it will wait on a nano timeout. Only
one task has to be able to record this information, since, these waits
being looping busy waits, the task of highest priority is the only task
that can be actively waiting with a nano timeout. If a task of lower
priority was previously waiting, and a new task is now waiting, it means
that the wait of the original task has been interrupted, which will
cause said task to run the busy loop on the object again when it gets
scheduled, and the number of ticks it wants to wait has to be recomputed
and recorded again.
Change-Id: Ibcf0f288fc42d96897642cfee00ab7359716703f
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Adds C++ support to the build system.
Change-Id: Ice1e57a13598e7a48b0bf3298fc318f4ce012ee6
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Adds extern "C" { } blocks to header files so that they can be
safely used by C++ source files.
Change-Id: Ia4db0c36a5dac5d3de351184a297d2af0df64532
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
We can save a great deal of RAM this way, it only needs to be
in RAM if dynamic interrupts are in use.
At some point this config option broke, probably when static
interrupts were introduced into the system.
To induce build (instead of runtime) errors when irq_connect_dynamic()
is used without putting the table in RAM, the dynamic interrupt
functions are now conditionally compiled.
Change-Id: I4860508746fd375d189390163876c59b6c544c9a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This adds driver for the UART controller on Atmel SAM3X8E.
This UART controller only has two wires for RX and TX, and
does not have flow control (e.g. CTS, RTS) or FIFO.
Currently, the driver does not support any interrupt driven
operations.
Change-Id: I63720bccfb70a89888353b8ee3dfc4b80793dc01
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds initial support for Atmel SAM3X8E processor, which is
based on ARM Cortex-M3. The SAM3X8E is being used on Arduino Due.
Change-Id: I199efcf29629f9ebacad474e5edc91bc3757f613
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This removes the default flash and SRAM base addresses from the ARM core
Kconfig file. Each individual SoC/processors Kconfig has to define them.
This is in preparation to support Atmel SAM3 family processors as they
have different base addresses.
Change-Id: I97ea9b43386d1e286ee692f583c97cfbb5399b0f
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This reverts commit 778d5b11c5327be4b40c7745e9beaecfd6327e13.
This patch has been identified as breaking the build when trying
to manually build non-x86 applications.
Change-Id: I1857745049dfef7193de58737108314b7aae01c5
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Decisions on compiler optimizations were done on the architecture level,
this does not scale and some SoCs will have different optimization levels
or compiler options needed. Moving this to the SoC makes it easy to optimize
differently when using the same CPU which we use to set the right optimization
now on the architecture level.
For IAMCU platforms, use the right architecture and tuning.
-march=lakemont -mtune=lakemont -miamcu -msoft-float
Change-Id: I0f77cffe7a139f8b2620935094437d0dfd160dfe
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The Kbuild system first looks for a Kbuild file, then it looks for
a make file.
Use the Kbuild for object building and leave the Makefile for definding
build options and compiler flags and other SoC related defines.
Change-Id: I0be59bb5ae02a29108a188efbd6f14dcdb7de4ee
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The interrupt API has been redesigned:
- irq_connect() for dynamic interrupts renamed to irq_connect_dynamic().
It will be used in situations where the new static irq_connect()
won't work, i.e. the value of arguments can't be computed at build time
- a new API for static interrupts replaces irq_connect(). it is used
exactly the same way as its dynamic counterpart. The old static irq
macros will be removed
- Separate stub assembly files are no longer needed as the stubs are now
generated inline with irq_connect()
ReST documentation updated for the changed API. Some detail about the
IDT in ROM added, and an oblique reference to the internal-only
_irq_handler_set() API removed; we don't talk about internal APIs in
the official documentation.
Change-Id: I280519993da0e0fe671eb537a876f67de33d3cd4
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
