Commit graph

604 commits

Author SHA1 Message Date
Julien Massot
f7e3f4f2d3 arch: arm: cortex_a_r: add support for arm arch timer
This include make possible to use the arm_arch_timer on
platform such as Cortex-A9 or Cortex-R7 which has support for
ARM Global Timer.

The global timer is a 64 bit incrementing counter, memory-mapped
in the private memory region.

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
2021-02-15 08:28:51 -05:00
Andy Ross
71fd58ccac drivers/cavs_timer: Fix multiword race with timer counter
The count register is 64 bits, but we're a 32 bit CPU that can only
read four bytes at a time, so a bit of care is needed to prevent
racing against a wraparound of the low word.  Wrap the low read
between two reads of the high word and make sure it didn't change.

Fixes #31599

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-02-04 13:10:25 -05:00
Flavio Ceolin
4ab6dd003e timer: arm: Mark ticks as unused
When TICKLESS_KERNEL is disabled the parameter ticks is not used.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2021-01-27 16:55:58 -05:00
Flavio Ceolin
cd0caced65 timer: arm: idle is used when CONFIG_TICKLESS_KERNEL
Only mark idle parameter unused when building without TICKLESS_KERNEL
enabled.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2021-01-27 16:55:58 -05:00
Flavio Ceolin
345849052a timer: arm: Fix idle usage option
idle is only considered in other timer implementations if ticks ==
K_TICKS_FOREVER but in arm_arch_timer. Just fix it.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2021-01-27 16:55:58 -05:00
Francois Ramu
1280e9817c drivers: timer: stm32 lptim fix Potentially overflow
Fix Unintentional integer overflow in the calculation
Integer handling issues (OVERFLOW_BEFORE_WIDEN)
Potentially overflowing expression

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2021-01-27 14:45:20 -05:00
Anas Nashif
c31ce55c58 timer: TICKLESS_CAPABLE is now without prompt
TICKLESS_CAPABLE is now selectable only and without prompt, so remove it
from _defconfig files and select it directly by the timer.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2021-01-21 22:51:19 -05:00
Flavio Ceolin
c408765d70 timer: legacy_api: Fix a build dependency in legacy_api header
z_timer_idle_enter is declared only when CONFIG_TICKLESS_IDLE is
selected. This function is not implemented anywhere, but the only
driver including this header is not TICKLESS_CAPABLE. So, no undefined
reference will happen.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2021-01-21 17:20:32 -05:00
Flavio Ceolin
1dd2d414b8 kernel: build: Make TICKLESS_CAPABLE a hidden option
TICKLESS_CAPABLE is an option that has to be selected by the target.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2021-01-21 17:20:32 -05:00
Giancarlo Stasi
af4c1cf58e drivers/timer: stm32_lptim: Fix stm32 ll header list
LPTIM stm32 ll header list was not adequate for debug builds.
Add _system.

Signed-off-by: Giancarlo Stasi <giancarlo.stasi.co@gmail.com>
2021-01-12 15:09:16 -06:00
Krzysztof Chruscinski
f3910fd716 drivers: timer: nrf_rtc_timer: Increase half tick busy wait
Due to clock discrepancy, busy waiting for 15us was not covering for
half tick in certain cases. Busy wait runs from HF clock source.

Increased to 19us to cover it. Anyway, this case is hit very rarely,
only when there was aborted, not-cancelled compare value that was
about to expire. Because of that, increase shall not impact the
performance.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2021-01-10 18:12:57 -05:00
Andy Ross
c2c6bee036 drivers/timer: Remove legacy APIC driver
For a while now, we've had two APIC drivers.  The older was preserved
initially as the new (much smaller, "new style") code didn't have
support for Quark interrupt handling.  But that's long dead now.  Just
remove it.

Note that this migrates the one board using this driver (acrn) to
CONFIG_APIC_TIMER instead.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2020-12-27 18:19:17 +01:00
Volodymyr Babchuk
35efb15637 arch: arm: timer: mask interrupt in ISR
As timer interrupt is level triggered, we need to mask it before leaving
ISR or it will be delivered again.

Also, Xen automatically masks timer interrupt when it injects IRQ to
a guest, so we need to unmask it again, when setting new timeout.

Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-12-17 08:08:00 -05:00
Cheryl Su
df6125f70d drivers/timer: it8xxx2 platform driver/timer
This commit is about the it8xxx2 timer driver.

We use the timer 5 as system timer for count time,
so the timer interrupt is trigged by it.

Signed-off-by: Cheryl Su <cheryl.su@ite.com.tw>
2020-12-16 08:47:36 -05:00
Alberto Escolar Piedras
fe516b93a9 board: native_posix: Add test for k_busy_wait and cpu_hold
Add a new test for k_busy_wait and cpu_hold

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
Signed-off-by: Wolfgang Puffitsch <wopu@demant.com>
2020-12-14 12:32:11 +01:00
Alberto Escolar Piedras
6d3476117b posix: Add cpu_hold() function to better emulate code delay
In native_posix and nrf52_bsim add the cpu_hold() function,
which can be used to emulate the time it takes for code
to execute.
It is very similar to arch_busy_wait(), but while
arch_busy_wait() returns when the requested time has passed,
cpu_hold() ensures that the time passes in the callers
context independently of how much time may pass in some
other context.

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2020-12-14 12:32:11 +01:00
Krzysztof Chruscinski
4def9a386b drivers: timer: nrf_rtc_timer: Fix non tickless sys clock handling
When tickless mode was disable, sys clock timeout handler was calling
public API function for setting new compare value. Public API function
asserts when chan 0 is used which is reserved for system clock.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2020-12-13 19:28:08 -05:00
Krzysztof Chruscinski
702f574dfd drivers: timer: nrf_rtc_timer: Fix comparison in z_nrf_rtc_timer_get_ticks
Test was failing due to wrong type conversion.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2020-12-13 19:28:08 -05:00
Krzysztof Chruscinski
b417f68609 drivers: timer: nrf_rtc_timer: Add clearing of previous CC event
Added clearing of CC event which may occure due to previous
CC value which was closed to current counter value.

Fixed int_mask initialization.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2020-12-13 19:28:08 -05:00
Joakim Andersson
a7fd4eab5c drivers: counters: Fix TIMER0 and RTC0 with Bluetooth controller
Fix TIMER0 and RTC0 being selectable when using out-of-tree Bluetooth
controller.
Generalize the Kconfig to have the features that use the HW peripheral
select them as reserved to make the dependencies more manageable.

Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
2020-12-13 19:25:49 -05:00
Anas Nashif
dd931f93a2 power: standarize PM Kconfigs and cleanup
- Remove SYS_ prefix
- shorten POWER_MANAGEMENT to just PM
- DEVICE_POWER_MANAGEMENT -> PM_DEVICE

and use PM_ as the prefix for all PM related Kconfigs

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2020-12-09 15:18:29 -05:00
Krzysztof Chruscinski
5b7fc3816d drivers: timer: nrf_rtc_timer: Fix int_mask initialization
Variable was not properly initialized when custom channels were
disabled.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2020-12-08 09:23:57 -05:00
Krzysztof Chruscinski
79e63b4216 drivers: timer: nrf: Extended driver with vendor specific API
Extended nrf_rtc_timer driver to expose API for using RTC for
other purposes. System timer is using one compare channels,
other channels may be used through this API.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2020-12-03 14:05:30 +01:00
Erwan Gouriou
e0b35dd0d5 drivers/timer: stm32_lptim: Fix stm32 ll header list
LPTIM stm32 ll header list was not adequate.
Remove _system and add _bus, _rcc and _pwr.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-12-01 17:59:53 -05:00
Martin Jäger
53af1aab62 drivers: timer: stm32_lptim: use generic LL headers
Use generic LL headers instead of depending on soc.h.

Signed-off-by: Martin Jäger <martin@libre.solar>
2020-11-30 15:50:03 +01:00
Martin Åberg
bb5a565aaa timer: Add support for GRLIB GPTIMER
This adds support for GRLIB GPTIMER general purpose timer used in
LEON3/4/5 systems.

One of the GPTIMER subtimers is used to generate periodic interrutps
for announcing ticks. Another subtimer is used as upcounter for the
cycle_get_32() service.

Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2020-11-13 14:53:55 -08:00
Trond Einar Snekvik
86c793af3f sys: util: Replace MIN(MAX(a, b), c) with CLAMP
Replaces all existing variants of value clamping with the MIN and MAX
macros with the CLAMP macro.

Signed-off-by: Trond Einar Snekvik <Trond.Einar.Snekvik@nordicsemi.no>
2020-11-05 12:12:17 +01:00
Andy Ross
ec6a98e5e1 drivers/timer/cavs_timer: Prevent spurious interrupts
The HDA wall clock timer is a 64 bit timer with 64 bit compare
registers, but it's being used from a 32 bit CPU.  Writing the
comparator piecewise with a 64 bit C assignment will write the low
dword first, opening the possibility that the hardware will see time
go "backwards" and trigger an interrupt incorrectly.

Disable the enable bit while setting the comparator.

Found by inspection.  In practice this will be very rare, and spurious
timer interrupts are supposed to be benign anyway (though they can
result in timeout expirations being misaligned to ticks, which might
be surprising to applications).  Best to get it right.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2020-10-21 06:38:53 -04:00
Krzysztof Chruscinski
ca786ce0ed drivers: timer: nrf_rtc_timer: Use interrupt priority from DT
Changed fix interrupt priority to the one from DT.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2020-10-06 15:34:34 +02:00
Krzysztof Chruscinski
c69a27b789 drivers: timer: nrf: Add configurable clock startup mode
Added configuration for approach to starting system clock source.
There are 3 options: no wait, wait untill available, wait until
stable.

Added support for those modes in clock control driver which handles
low frequency source clock.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2020-09-10 21:31:01 +02:00
Kumar Gala
184a25769c arm: systick: default CORTEX_M_SYSTICK based on dts
Use setting from devicetree to drive the default setting for
CORTEX_M_SYSTICK.  We update the dts files to default systick to be
enabled since the major of cortex-m platforms utilize it by default
(except on Nordic SoCs, TI CC13x2/CC26x2 and MEC1501 in which we
default to disabled).

Fixes #25299

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-09-10 09:49:00 +02:00
Anas Nashif
6e27478c3d benchmarking: remove execution benchmarking code
This code had one purpose only, feed timing information into a test and
was not used by anything else. The custom trace points unfortunatly were
not accurate and this test was delivering informatin that conflicted
with other tests we have due to placement of such trace points in the
architecture and kernel code.

For such measurements we are planning to use the tracing functionality
in a special mode that would be used for metrics without polluting the
architecture and kernel code with additional tracing and timing code.

Furthermore, much of the assembly code used had issues.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2020-09-05 13:28:38 -05:00
Tomasz Bursztyka
4dcfb5531c isr: Normalize usage of device instance through ISR
The goal of this patch is to replace the 'void *' parameter by 'struct
device *' if they use such variable or just 'const void *' on all
relevant ISRs

This will avoid not-so-nice const qualifier tweaks when device instances
will be constant.

Note that only the ISR passed to IRQ_CONNECT are of interest here.

In order to do so, the script fix_isr.py below is necessary:

from pathlib import Path
import subprocess
import pickle
import mmap
import sys
import re
import os

cocci_template = """
@r_fix_isr_0
@
type ret_type;
identifier P;
identifier D;
@@
-ret_type <!fn!>(void *P)
+ret_type <!fn!>(const struct device *P)
{
 ...
(
 const struct device *D = (const struct device *)P;
|
 const struct device *D = P;
)
 ...
}

@r_fix_isr_1
@
type ret_type;
identifier P;
identifier D;
@@
-ret_type <!fn!>(void *P)
+ret_type <!fn!>(const struct device *P)
{
 ...
 const struct device *D;
 ...
(
 D = (const struct device *)P;
|
 D = P;
)
 ...
}

@r_fix_isr_2
@
type ret_type;
identifier A;
@@
-ret_type <!fn!>(void *A)
+ret_type <!fn!>(const void *A)
{
 ...
}

@r_fix_isr_3
@
const struct device *D;
@@
-<!fn!>((void *)D);
+<!fn!>(D);

@r_fix_isr_4
@
type ret_type;
identifier D;
identifier P;
@@
-ret_type <!fn!>(const struct device *P)
+ret_type <!fn!>(const struct device *D)
{
 ...
(
-const struct device *D = (const struct device *)P;
|
-const struct device *D = P;
)
 ...
}

@r_fix_isr_5
@
type ret_type;
identifier D;
identifier P;
@@
-ret_type <!fn!>(const struct device *P)
+ret_type <!fn!>(const struct device *D)
{
 ...
-const struct device *D;
...
(
-D = (const struct device *)P;
|
-D = P;
)
 ...
}
"""

def find_isr(fn):
    db = []
    data = None
    start = 0

    try:
        with open(fn, 'r+') as f:
            data = str(mmap.mmap(f.fileno(), 0).read())
    except Exception as e:
        return db

    while True:
        isr = ""
        irq = data.find('IRQ_CONNECT', start)
        while irq > -1:
            p = 1
            arg = 1
            p_o = data.find('(', irq)
            if p_o < 0:
                irq = -1
                break;

            pos = p_o + 1

            while p > 0:
                if data[pos] == ')':
                    p -= 1
                elif data[pos] == '(':
                    p += 1
                elif data[pos] == ',' and p == 1:
                    arg += 1

                if arg == 3:
                    isr += data[pos]

                pos += 1

            isr = isr.strip(',\\n\\t ')
            if isr not in db and len(isr) > 0:
                db.append(isr)

            start = pos
            break

        if irq < 0:
            break

    return db

def patch_isr(fn, isr_list):
    if len(isr_list) <= 0:
        return

    for isr in isr_list:
        tmplt = cocci_template.replace('<!fn!>', isr)
        with open('/tmp/isr_fix.cocci', 'w') as f:
            f.write(tmplt)

        cmd = ['spatch', '--sp-file', '/tmp/isr_fix.cocci', '--in-place', fn]

        subprocess.run(cmd)

def process_files(path):
    if path.is_file() and path.suffix in ['.h', '.c']:
        p = str(path.parent) + '/' + path.name
        isr_list = find_isr(p)
        patch_isr(p, isr_list)
    elif path.is_dir():
        for p in path.iterdir():
            process_files(p)

if len(sys.argv) < 2:
    print("You need to provide a dir/file path")
    sys.exit(1)

process_files(Path(sys.argv[1]))

And is run: ./fix_isr.py <zephyr root directory>

Finally, some files needed manual fixes such.

Fixes #27399

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2020-09-02 13:48:13 +02:00
Tomasz Bursztyka
e18fcbba5a device: Const-ify all device driver instance pointers
Now that device_api attribute is unmodified at runtime, as well as all
the other attributes, it is possible to switch all device driver
instance to be constant.

A coccinelle rule is used for this:

@r_const_dev_1
  disable optional_qualifier
@
@@
-struct device *
+const struct device *

@r_const_dev_2
 disable optional_qualifier
@
@@
-struct device * const
+const struct device *

Fixes #27399

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2020-09-02 13:48:13 +02:00
Flavio Ceolin
e1e4a402e2 drivers: timer: Explicitly setting argument as unused
Marking as unused (ARG_UNUSED) the parameter device in the
initialization function z_clock_driver_init when it is not used.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2020-08-27 07:02:40 -04:00
Andrew Boie
63c3e153d6 drivers: use node IDs for DEVICE_MMIO.*_INIT
There is nothing wrong with instance numbers and they are
recommended for use whenever possible, but this is an API
design problem because it's not always possible to get nodes
by instance number; in some cases, drivers need to get node
identifiers from node labels, for example.

Change these APIs (which are not yet in any Zephyr release)
to take node IDs instead of instance IDs.

Fixes: #26984

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-08-14 13:35:02 +02:00
Carles Cufi
244f826e3c cmake: remove _if_kconfig() functions
This set of functions seem to be there just because of historical
reasons, stemming from Kbuild. They are non-obvious and prone to errors,
so remove them in favor of the `_ifdef()` ones with an explicit
`CONFIG_` condition.

Script used:

git grep -l _if_kconfig | xargs sed -E -i
"s/_if_kconfig\(\s*(\w*)/_ifdef(CONFIG_\U\1\E \1/g"

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2020-08-01 12:35:20 +02:00
Krzysztof Chruscinski
2881df3d0c drivers: timer: nrf: Adapt to clock_control changes
Adapted driver to clock_control changes (usage of onoff manager).
Since timer is permanenty requesting the clock, it is using API
dedicated for that: z_nrf_clock_control_lf_on().

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2020-07-20 16:22:21 +02:00
Andrew Boie
7f7d05c262 drivers: hpet: use device_mmio
Straightforward example on how to use the TOPLEVEL variants
of the DEVICE_MMIO macros.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-07-17 11:38:18 +02:00
Pawel Dunaj
af063ccd12 drivers: timer: nrf_rtc: Use correct macro when capping cycles
When checking the absolute value of cycles set to the comparator
use the MAX_CYCLES instead of MAX_TICKS.

The commit changes function names and comments to make it clear
where ticks (system ticks) and where RTC cycles are used.

Fixes #26701

Signed-off-by: Pawel Dunaj <pawel.dunaj@nordicsemi.no>
2020-07-08 12:33:08 +02:00
Sandeep Tripathy
b37ce93979 drivers: timer: fix tickless contineous interrupts
K_FOREVER/INT_MAX number of ticks needs delay cycles value of
maximum order and exceeds 'int32' range.
The typecast to 'int32' results in wrongly evaluating the value
as less than 'MIN_DELAY' and chooses 'MIN_DELAY' over the actual
delay cycles.

Cap the 'MAX_TICKS' to INT32_MAX.

fixes: #26632
Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
2020-07-07 15:06:55 +02:00
0bc3585800 drivers: timer: enable read synchronisation mode for the SAMD/E5x
The COUNT register on the SAMD/E5x RTC can only be read if the read
synchronisation mode is enabled.

Signed-off-by: Michael Hope <mlhx@google.com>
2020-07-03 12:20:03 -04:00
89466d57ea drivers: timer: fix the use of K_FOREVER for the SAMD/E5x
Change K_FOREVER for K_TICKS_FOREVER.

Signed-off-by: Michael Hope <mlhx@google.com>
2020-07-03 12:20:03 -04:00
Andy Ross
b466e579a3 drivers/timer/hpet: Disable FSB interrupts
The front side bus interrupt delivery feature is a somewhat obscure
part of PC history (in some sense a presaging of MSI interrupts) that
we don't use.

But it's part of the spec, works on hardware, has precedence over the
"legacy" interrupt routing feature we do use, and can be legally
enabled by firmware.

Disable at init time.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2020-06-30 21:37:54 -04:00
Giancarlo Stasi
259b30016b drivers: timer: stm32 lptim minor fix and optimization
Avoid reading LPTIM counter four times instead of three when second
read doesn't give same value. Use common code, avoid volatile for
local vars.

Signed-off-by: Giancarlo Stasi <giancarlo.stasi.co@gmail.com>
2020-06-23 19:05:16 +02:00
Daniel Leung
afc1b9de13 timer: hpet: enable level triggering
The HPET timer was hard-coded to support only edge triggering
interrupts. This adds the necessary bits to enable level
triggering for the timer.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2020-06-16 10:52:43 -05:00
Francois Ramu
0856e99155 drivers: timer: stm32 lptim stops counting on timeout FOREVER
When setting a timeout K_TICKS_FOREVER,the lptimer clock is stopped
(no reset of the lptim).
Then is the lptim possibly re-started when another source asks for.
The lptim clock must then be re-started and continue counting.
This is the case when wakeup from sleep mode, for example.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2020-06-10 09:33:40 -05:00
Aurelien Jarno
e4b62a8ce2 drivers: timer: lptim: depend on SYS_POWER_MANAGEMENT
The LPTIM driver is supposed to be only available when the SoC is
allowed to enter power sleep mode, as described in commit f30f5fff72
("drivers: timer: lptim is [EXPERIMENTAL] for stm32 soc series only").

For that it should depends on SYS_POWER_MANAGEMENT (which gates the
SYS_POWER_SLEEP_STATES and SYS_POWER_DEEP_SLEEP_STATES options) instead
of DEVICE_POWER_MANAGEMENT.

Fixes #25989

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2020-06-09 08:15:56 -04:00
Kumar Gala
a1b77fd589 zephyr: replace zephyr integer types with C99 types
git grep -l 'u\(8\|16\|32\|64\)_t' | \
		xargs sed -i "s/u\(8\|16\|32\|64\)_t/uint\1_t/g"
	git grep -l 's\(8\|16\|32\|64\)_t' | \
		xargs sed -i "s/s\(8\|16\|32\|64\)_t/int\1_t/g"

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-06-08 08:23:57 -05:00
Julien D'Ascenzio
37e50a6775 driver: timer: stm32_lptim: fix excess ticks
Some ticks are counted additionally when the autoreload
interrupts were too close together.
This patch improve the counts of the clock cycle.
lptim_fired worked badly in particular because the flag ARRM
was not raised when the interrupt was forced.

Signed-off-by: Julien D'Ascenzio <julien.dascenzio@paratronic.fr>
2020-06-04 22:10:45 +02:00