Page tables created at build time may not include the
gperf data at the very end of RAM. Ensure this is mapped
properly at runtime to work around this.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Pre-allocation of paging structures is now required, such that
no allocations are ever needed when mapping memory.
Instantiation of new memory domains may still require allocations
unless a common page table is used.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We no longer use a page pool to draw memory pages when doing
memory map operations. We now preallocate the entire virtual
address space so no allocations are ever necessary when mapping
memory.
We still need memory to clone page tables, but this is now
expressed by a new Kconfig X86_MAX_ADDITIONAL_MEM_DOMAINS
which has much clearer semantics than specifying the number
of pages in the pool.
The default address space size is now 8MB, but this can be
tuned by the application.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Just tell the kernel that RAM starts 1MB in, period.
Better simulation of a low-memory microcontroller as
we're not managing a very large number of page frames
we'll never use.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Previously, newlib claimed all free physical memory in the
system.
Now, the kernel manages this, allowing for memory to be
used via k_mem_map() calls.
Establish an upper bound to how much newlib will try to
claim on system startup, instead of trying to take all
of it, allowing other parts of the system to also map
anonymous memory.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We now draw heap memory from an anonymous memory mapping
instead of a hard-coded region past the kernel image,
which is no longer mapped by default.
Some readability cleanups were made to a particuarly
horrible set of nested ifdefs. A few types were adjusted.
sbrk()'s count argument is an intptr_t, not an int.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
All RAM may not be mapped. Check the mapping for the main kernel
image and the locore if it exists.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
A more comprehensive solution would use E820 enumeration, but we
are unlikely to ever care that much, as we intend to use demand
paging on microcontrollers and not PC-like hardware. This is
really to just prevent QEMU from crashing.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Allows applications to increase the data space available to Zephyr
via anonymous memory mappings. Loosely based on mmap().
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Add linker symbols corresponding to the start and end of the
mapped Zephyr image. This is not used by the ARM arch yet, but
is required to compile the core kernel MMU code.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We will use this to map the kernel instead of all RAM.
The end of the kernel is always page-aligned, regardless
of CONFIG_SRAM_REGION_PERMISSIONS as it must be mapped.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
These are needed on MMU systems and define where the kernel
image resides in virtual memory at boot so that it may be
memory-mapped.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This is only needed if the base address of SRAM doesn't
have the same alignment as the base address of the virtual
address space.
Fix the calculations on X86 where this is the case.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Coded PHY is only enabled by default if the application is using
BT_HCI_RAW.
Coded PHY is not needed in most applications.
By disabling Coded PHY, most applications will:
* Get smaller in terms of flash and ram usage
* Not get vurnerable to devices trying to switch to Coded and
thereby increasing power consumption.
Signed-off-by: Rubin Gerritsen <rubin.gerritsen@nordicsemi.no>
Use TX FIFO level interrupt if available in hardware. It matches the
Zephyr UART API and avoids "bootstrapping" which is needed when using
the TX edge interrupt ("TI"). TX FIFO has room for up to 32 characters
and will typically reduce the number of interrupts.
Details:
APBUART can be synthesized with or without support for TX/RX FIFO.
Edge interrupts which fire when TX holding register changes and RX data
available are always available, independent of the FIFO configuration.
If FIFO is made available at synthesis time, two additional interrupts
become available: TX FIFO half-empty and RX FIFO half-full. These
are level interrupts.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
This commit aligns the GRLIB APBUART driver with the Zephyr UART API
and fixes an issue where TX interrupt could previously be lost. It
was typically seen during interactive operation in the Zephyr shell.
There is an expectation in the Zephyr UART API that TX ready (i.e. TX
buffer space available) interrupt is a level interrupt, i.e. always
active while there's TX buffer space available. In particular, there's
an expectation that after uart_irq_tx_enable(), the TX interrupt will
immediately fire (assuming free TX buffer space is available).
The APBUART "Transmitter interrupt (CTRL_TI)" does not directly fulfill
this expectation because it is edge triggered and fires when the TX
holding register moves from being non-empty to empty. The solution
is to "bootstrap" interrupt processing by calling user-defined ISR
in irq_tx_enable().
This fix is similar to commit 49bb163756 ("drivers: serial:
uart_cmsdk_apb: Fix interrupt-driven operation").
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
Refactor the output of device list to use standard API to retrieve the
list of devices, and to always display a status rather than hiding
disabled/failed devices.
Add API to associate a distinct identifier with any "device" that does
not have a name.
Where a device has requires dependencies display the devices on which
it depends.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Following the idiom used for system calls, add script support to read
the initial application binary to identify which devices are defined,
and to use their offset in the device array as their unique handle
rather than the externally-defined ordinal from devicetree. The
device dependency arrays are updated to use these handles.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Generate arrays of dependency information for each device. If a
device definition is being constructed from devicetree these come from
the devicetree dependency information. Additional dependencies may be
passed through using the DT_ macros.
Define flag values for device handles so we can partition the
dependency array into distinct sets, which include things it requires,
things it supports (may not be needed), and child nodes (not
implemented, may not be needed).
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
These need to be gpio controllers and have the necessary specifier
properties for use in gpio specifiers.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Add board support files for mimxrt1024_evk, the development board for
i.MXRT1024(CM7) SoC.
- Add pinmux, dts, doc.
- Code can be loaded to SRAM.
- Tested samples: hello_world, philosophers, synchronization,
basic/blinky, and basic/button.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Macros like INT64_C(x) convert x to a constant integral expression,
i.e. one that can be used in preprocessor code. Implement wrappers
that use the GNUC intrinsics to perform the translation.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
zephyr/types.h does not belong as a dependency for testing a C library
implementation of stdint. Use the toolchain file directly.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Fix kernel.common and kernel.common test cases fail due to build error
in platform intel_adsp_cavs15, 18, 20, 25.
Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
The driver allocated packet from the TX pool on its RX path. Fix this
by using a correct allocator function.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
Timer 1 has two interrupts on STM32F0: TIM1_BRK_UP_TRG_COM_IRQn (13) and
TIM1_CC_IRQn (14). "brk" interrupt name does not reflect all the events
supported by the interrupt, so it has been renamed to "brk_up_trg_com".
On all other series except G0 timer 1 has a specific interrupt for each
event, so in such case "brk" is just fine.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add LED and switch DTS information. Port P0 received the NVIC line 20
on Cortex-M0+ cpu. This way, SW_0 switch can be connected as external
interrupt source for both m0 and m4 cpus.
Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
Add LED and switch DTS information. Port P0 received the NVIC line 20
on Cortex-M0+ cpu. This way, SW_0 switch can be connected as external
interrupt source for both m0 and m4 cpus.
Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
Not all I2C controllers that support dual roles allow a controller to
be used in both modes without reconfiguration: for some, registering a
slave device prevents use in master mode. Refactor so that dual-role
operation is opt-in, and select it for the ST devices currently in the
allow list.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Reduce the verbosity of the I2C log messages; we don't need to see
every transaction by default.
In the application replace use of the log infrastructure with TCPRINT,
and remove some messages that don't seem to be necessary.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
ESP chip send number of available RX data using
+IPD=<sock>,<avail_bytes> command. This exact number (truncated to MRU)
was used to read data with AT+CIPRECVDATA=<sock>,<num_of_bytes>.
Use always MRU when sending AT+CIPRECVDATA=<sock>,<mru> request. When
there are less bytes available, then +CIPRECVDATA will just return less
bytes, which is fine for the driver.
There are two advantages to this new behavior:
* there is no need to follow how many bytes were notified by +IPD
message, thus reducing implementation size,
* when data is constantly received by ESP chip, then the last number of
bytes notified by +IPD is no longer up-to-date when sending a
AT+CIPRECVDATA; always requesting MRU number of bytes allows to
always receive maximum currently available number of bytes buffered
by ESP chip.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Dump of communication between ESP chip and Zephyr shows that
+IPD:<sock>,<bytes_avail> is always received after +CIPRECVDATA. This
means that we don't need to update sock->bytes_avail in esp_workq
thread. Additionally there is no need to schedule next AT+CIPRECVDATA
request, as that will be done by +IPD handler anyway.
Relying on +IPD to be received after each +CIPRECVDATA (as long as there
is some more data to be received) allows to simplify operations on
sock->bytes_avail. From now on only esp_rx thread will update its value
and schedule AT+CIPRECVDATA in esp_workq thread. Then in
sock->bytes_avail will be treated as "readonly" in esp_workq
thread. This allows to prevent race condition when both esp_rx and
esp_workq threads could potentially update value of sock->bytes_avail
value at the same time.
<sock>,CLOSED message is received always after retrieving all data from
ESP chip (using AT+CIPRECVDATA), so there is no need to check whether
there are more bytes to be received before marking socket as closed in
Zephyr driver.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
