This was only needed for the older 8259A style PICs which are no
longer supported.
Since we now just support APIC, we always just call loapic_eoi which
no longer requires an argument and informs the IOAPIC that the interrupt
is complete if necessary.
Change-Id: I15c9b7b4f03b872656220af32220b62e043bfa6b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This patch enables defining microkernel events within source code.
This is similar to other private kernel object patches.
The test has been modified a little bit due to the fact that
the event ID is now a memory address, instead of numeric ID.
Change-Id: Ie3c8d4f4e459d9c631e50bb242cf7a05ca8ea82c
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Updates the 'gen_idt' tool to generate a mapping of IRQ numbers to
interrupt vector IDs, thereby allowing the IRQ priority to be utilized
when statically connecting an interrupt.
Change-Id: I2e54ceb65145682820dfbd8ca1ee6ec68d71ce1a
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Change-Id: Ie051000e3d3f0f5bdc330d0265010c37acb873bd
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Change-Id: I819d13f0d7a23e3a61dcda6a3ced18810b192158
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Change-Id: I6da43e41f9c6efee577b70513ec368ae3cce0144
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Updates several files to remove mention of Diab toolchain
support, which is no longer supported. These changes do not
affect system operation.
Change-Id: If9de85e595f6685295e565bc94ca17f51d87513f
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
In order to have drivers that are usable cross architecture the
signature for IRQ_CONFIG needs to be the same to avoid #ifdef hell in
the driver code based on architecture.
Update the macro and it usage for existing drivers
Change-Id: I22e142b21d4e984add231d1dbd97020e4823985f
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Introduces the SYS_DEFINE_DEVICE() macro, which supports 5 distinct
levels of device initialization and 100 priorities within each level.
Note: The existing init macros (e.g. nano_early_init()) have been
adapted to utilize the enhanced initialization model, but will
eventually be retired.
Change-Id: If677029d8b711a3fae9b2f32b5470cd97d19aeda
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
Drivers do it by themselves, usually either in a dedicated irq
configuration function or direcly in their initialization routine.
Change-Id: Id1cca1a1e3e3f36264d99d1d2f2d651d84e0687e
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This functions - reusing _arc_v2_aux_reg_* ones - will ease porting
drivers to ARC architecture hiding arch specific calls under generic
functions. On ARC, auxiliary registers is conceptually comparable to
x86 ports, thus the possibility to bring sys_in/sys_out to access those.
Change-Id: Ic5c0fc41f32ec4ad861dbb58cd8defaf4497bc03
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Change all the Intel and Wind River code license from BSD-3 to Apache 2.
Change-Id: Id8be2c1c161a06ea8a0b9f38e17660e11dbb384b
Signed-off-by: Javier B Perez Hernandez <javier.b.perez.hernandez@linux.intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Updates the 'gen_idt' tool to generate a bitmap of (statically) allocated
interrupt vectors that is linked into the final image in a manner similar to
the static IDT. The kernel then uses this bitmap when dynamically connecting
an interrupt vector, thereby preventing the dynamic irq connections
from clobbering the static irq connections.
Change-Id: I0a8f488408dad4912736865179f32f63ff1ca98f
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Adds two new fields to the ISR_LIST structure (irq and priority) to allow
the decoupling of the vector ID and priority from the IRQ number at some
future time.
As a result of the addition of these two new fields, the gen_idt tool is
modified to both process these new fields as well as validate them.
Change-Id: I343dac68d99c78168a25b19784140f85d5db7578
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Fixes a bug in the x86 IRQ_CONNECT_STATIC() macro that resulted in setting
the DPL for the interrupt to the IRQ priority level.
Note 1: Using a proper value for the DPL (instead of the priority) prevents
the corruption of the other IDT fields.
Note 2: The priority of the IRQ is completely ignored.
Change-Id: Ic9f59bd91db4b356263f533cc26a0168b1d236e1
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
We are seeing on some platforms that the VMA alignment
does not match the LMA alignment for this section, resulting
in problems when copying into RAM by __csSet(); any copied
sections afterwards end up misaligned in RAM.
While the true fix for this is under investigation, force
4-byte alignment for VMA and LMA.
Change-Id: I627d9e7a3446cbc09dc310a156d8b3268e61c91d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Due to similar padding issue as pipe, the list of task object
may not be used directly. As mentioned before, some compiler/linker
may pad the large struct. For example, compiling under gcc and
march=i686 pads the struct to 32-byte alignment (march=atom to
64-byte alignment). This causes issue with sizeof() and pointer
arithmetic because they have no idea about the padding.
When the stars align in a certain way, these task structs may be
corrupted. So add a task pointer list and use it for task
manipulation. The task list remains as it is beneficial to group
them together to take advantage of cache locality.
Change-Id: I0e86bfe05742040f4540d7854c1ac14e76162776
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit fixes small errors on the asm implementation of arc
register reading and the built-in functions call.
Change-Id: Iea2df715eaefb25095770971ac03d441311abf16
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
The _ARC_V2_IRQ_VECT_BASE register must be set to the vector table in
flash.
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
Change-Id: Ied5451c98222f545cd669967023aef26c3d8e48e
- Finally switched from ldw/stw to ldh/sth, as Benjamin noticed in an
earlier comment (I was using ARC ISA, and not ARC V2 ISA). So indeed
ldw/stw are obsolete and equivalent to ldh/std.
- clear, set and test were not working in case of using a memory address
which would not point to a register: bclr, bset and btst requires
registers as operands, and cannot deal with pure memory address (i.e.
something like [rx] is not valid), thus the requirement to load first
the value pointed by the address into a register, operate on that
register and storing the result of it into the pointed address.
Change-Id: Ib9c24c0a2c6d2b02e2d08d24f31cbc1981536a7d
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Doxegenize and cleanup headers for nanokernel
- fibers
- context
- timers
- stacks
Also minor cleanup of x86/arch.h
Change-Id: Ib65568d4ec034b69e8a6214ba4b52a7f719300bb
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
sys_in/sys_out are not implemented as there is no "ports" in ARC.
Change-Id: Ie72d6274ae1a2b2ca22955a9764e281e7669b973
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This will be helpful also in drivers mostly, where non-atomic bit
setting could be unnecessary.
Change-Id: I10c069387d1045f14337b3ac8acfc7b6c1f106c3
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
sys_io.h header file declares the generic API for such operations. It
properly separates port and memory mapped registers, with declaring
respective types: io_port_t and mm_reg_t.
Memory mapped registers are the most common type of registers drivers
will play with. Thus providing generic sys_readX/sys_writeX functions in
sys_io.h. Those are defined as inline as they are really simple.
Ports are mostly (always?) found in x86 architecture.
Currently no ARM or ARC header file propose any implementation of
those. If really necessary (a cross-architecture driver using
sys_in/sys_out functions), those architecture will provide the proper
implementation or at least a macro gluing those towards
sys_read/sys_write.
Change-Id: If77590d4bcefcdfa6aa181a88ced342f8565d5b8
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The term 'context' is vague and overloaded. Its usage for 'an execution
context' is now referred as such, in both comments and some APIs' names.
When the execution context can only be a fiber or a task (i.e. not an
ISR), it is referred to as a 'thread', again in comments and everywhere
in the code.
APIs that had their names changed:
- nano_context_id_t is now nano_thread_id_t
- context_self_get() is now sys_thread_self_get()
- context_type_get() is now sys_execution_context_type_get()
- context_custom_data_set/get() are now
sys_thread_custom_data_set/get()
The 'context' prefix namespace does not have to be reserved by the
kernel anymore.
The Context Control Structure (CCS) data structure is now the Thread
Control Structure (TCS):
- struct ccs is now struct tcs
- tCCS is now tTCS
Change-Id: I7526a76c5b01e7c86333078e2d2e77c9feef5364
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
The files idtEnt.h and segselect.h in shared are linked from
the source tree for no good reason adding and extra top level
directory that might be confusing.
The shared/ here means shared between host and target, this is
not longer necessary in our build system.
Change-Id: Id9665e10de7a1d290888d9069be3db9f4330d284
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Highlight the fact that find_[lsb|msb]_set operate on a 32-bit word.
Change-Id: I24cee7709ea6497508dbc7f96a7b4d74fa4bc257
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
The new names reflect better what the functions do: they find the first
bit set starting from the least or most significant bit, i.e. they find
the least or most significant bit set, in a 32-bit word.
Change-Id: I6f0ee4b543f6f37c2f08f7067e14e039c92a6f6a
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
The inline versions are renamed to remove the _inline suffix, and the
non-inline versions are removed from the code base.
Change-Id: Iee2e6adcfb5da1fe0a978a05aa854e10ae82a8b8
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
The inline versions are renamed to remove the _inline suffix, and the
non-inline versions are removed from the code base.
Change-Id: I7314b96c42835f15df4c537ec11ab7961d4ee60f
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
irq_handler_set, irq_priority_set and irq_disconnect have been made
private by prepending an underscore to their names:
irq_handler_set -> irq_handler_set
irq_priority_set -> irq_priority_set
irq_disconnect -> irq_disconnect
The prototypes have been removed from header files when possible, and
extern statements used in C code where they were called.
_irq_priority_set() for ARM is still in the header file because
IRQ_CONFIG() relies on it.
Change-Id: I2ad585f8156ff80250f6d9eeca4a249a4477fd9d
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
