General refactoring to clean up and futureproof this driver.
Remove false dependency on CONFIG_CAVS_ICTL. This requires the CAVS
interrupt mask API, but doesn't touch the interrupt controller driver.
Remove a racy check for simultaneous interrupts. This seems to have
been well intentioned, but it's needless: the spinlock around the
last_count computation guarantees that colliding interrupts will
correctly compute elapsed ticks (i.e. the last will compute and
announce zero ticks, which is correct and expected). And this opened
a tiny window where you could incorrectly ignore a just-set timeout.
Factor out the specific registers used (there are only five) into
pointer-valued macros instead of banging them directly.
Unify interrupt initialization for main and auxiliary cores.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
When running under a simulator, it's difficult to extract output from
the window (it's difficult with hardware too!). Add "SIMCALL" output
to stderr (it's literally just 3 extra instructions) as an optional
feature so this subsystem itself can be debugged without herculean
effort.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Reword the symbols to make it clear what they mean ("INIT_LPSRAM"
instead of "RESET_MHE_AT_BOOT") and use them correctly instead of
SOC_SERIES_* kconfigs.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
We don't define a MemoryException handler, nor is one appropriate for
this hardware as it stands. And the empty section keeps causing
linker warnings we have to work around. Remove.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Single-core instantiations of this hardware and single-core builds of
firmware still exist, so we should support that without needless
bloat.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The MP startup code had a hardcoded INTLEVEL field of 5 in the initial
value of PS. That's needless, INTLEVEL is a full 4 bit field even if
the number of hardware interrupt levels is lower (and in fact 0xf is
the documented hardware reset state). Set that instead, so that this
code will work with any XEA2 hardware. This also matches the similar
code path in boot startup.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Most of soc.c is actually interrupt handling glue for the intc_cavs
driver. Give it its own file so that SOC initialization and bringup
can live separately.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Instead of using maskstatus to see if an interrupt has fired,
use finalstatus instead. It has been observed that some
controllers do not update maskstatus correctly with incoming
interrupts, but finalstatus works fine.
FYI, the DW driver in Linux is also using finalstatus.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
It is documented as unsigned in
samples/net/sockets/big_http_download/Kconfig
Signed overflow is undefined behavior, unsigned is not. This fixes the
following warning:
-Wstrict-overflow=1
samples/net/sockets/big_http_download/src/big_http_download.c:346:2:
In function 'main':
error: iteration 2147483648 invokes undefined behavior
[-Werror=aggressive-loop-optimizations]
346 | } while (--num_iterations != 0);
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Excluded due to conflicts with adafruit_2_8_tft_touch_v2.
Both boards got a touch controller.
Signed-off-by: Konstantinos Papadopoulos <kostas.papadopulos@gmail.com>
Recent changes in this function made the code now compatible
with the use of LL API to perform this configuration.
Use it to simplify the driver.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
When logging is using immediate mode then logging messages
can be processed from any context, including interrupt context.
z_shell_fprintf was asserting in that case since it allowed to
be called from interrupt context only when logging was in panic
mode. However, shell works in the same way when logging is in
immediate mode as in panic mode.
Renamed internal shell flag from panic_mode to sync_mode. Flag
is also set when shell log backend is started in synchronous
mode (immediate logging) which prevents assertion.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Fix hard fault due to NULL being passed as argument into
rssi_handler, which now derives the gsm_modem struct pointer from
the argument.
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
XCHAL_HAVE_ICACHE_DYN_ENABLE is not set for any Intel cAVS
hardware, so MEMCTL configuration is not done properly leaving
icache disabled. This can be seen as ~10X slowness when running
code on non-primary cores. Fix the issue by using XCHAL_USE_MEMCTL
to check for MEMCTL usage.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
When message is dropped then log_process is called with
bypass flag set and additionally z_log_dropped() is called.
In both functions counter of buffered messages was decremented.
That resulted in counter being decremented twice. It resulted
in logging misbehavior after messages being dropped (delayed
processing). Fixing it by decrementing the counter in log_process
only when bypass flag is not set.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Use value returned by atomic_inc to decide on action.
Previously direct value was used and that could lead to
delays in logging processing because thread waking up
could be mishandled.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Only consider negative statuses returned from a L2CAP server as error.
This makes the status check done here consistent with the check done in
l2cap_chan_le_recv_sdu.
Signed-off-by: Abe Kohandel <abe.kohandel@gmail.com>
Adding #ifndef CONFIG_LOG2 condition for log_msg_ids and
log_string_sync in sys-t sample. Extending support for
v2 logging in sys-t sample.
Signed-off-by: Aastha Grover <aastha.grover@intel.com>
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Adding functions log_output_msg2_syst_process and hexdump2_print
to support v2 logging subsystem.
Updates west.yml to pick up a new version of the MIPI sys-t library that
supports vprintf.
Signed-off-by: Aastha Grover <aastha.grover@intel.com>
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
The signature of bt_mesh_app_key_resolve expresses pointer to a 16 byte
array as a const uint8_t *app_key[16], which is actually an array of 16
byte pointers. The intended type is equivalent to a double pointer to
const uint8_t, but trips up GCC 11, which actually checks this.
Signed-off-by: Trond Einar Snekvik <Trond.Einar.Snekvik@nordicsemi.no>
The crypto.h declaration of the bt_mesh_beacon_auth function declares
the net_id parameter to be a 16 byte array, but the function definition
says 8 bytes. This breaks compilation in GCC 11, which feeds an 8 byte
array into this API, triggering a warning. Change the header declaration
to 8 bytes, which is the right size.
Signed-off-by: Trond Einar Snekvik <Trond.Einar.Snekvik@nordicsemi.no>
New Sphinx version (or docutils) has slightly changed the output format
for code documentation directives. These changes try to mimic previous
behavior, even though it does not achieve 100% equal result. In some
cases the new default style does not require further tweaks, and in some
others styling as before is not possible.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
breathe: for simplicity, require versions > 4.30 (lower versions have
known issues, so do not take risks).
Sphinx: start requiring versions >=4.x. Keep with compatible versions,
since Sphinx major updrages can easily break extensions, themes, etc.
sphinx_rtd_theme: upgrade to >=1.x. Again, keep with compatible versions
since we have style customizations that can likely break on major
upgrades.
pygments: Allow any version >=2.9 (version that introduced DT support).
We do not have strong compatibility requirements here.
sphinx-notfound-page: Remove any requirements, we do not have strong
requirements for this one.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The docstring for this function states that it is guaranteed to perform
a copy byte by byte, but this is not true in general without a
`volatile` storage type on the casted pointer.
Signed-off-by: Chris McDonald <cjmcdonald@chromium.org>
Disabling clock may conflict with concurrent usage of GPIOs and pins in
AF mode. This can be improved once a proper clock control API is in
place.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add DT overlay to run gpio_basic_api test on GD32F403Z-EVAL board. In
order to make testing easy a couple of accessible pins have been
selected: PD0 and PD1 pins exposed via P3 and P2 respectively.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add DT overlay to run gpio_basic_api test on GD32F450I-EVAL board. In
order to make testing easy a couple of accessible pins have been
selected: PC6 and PC7, the last 2 pins on the DCI camera 2.54" header.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add definitions for board LEDs and keys now that a GPIO driver exists.
The GPIO driver has also been enabled in the board defconfig, since it
is required to run some basic samples (e.g. blinky).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add definitions for board LEDs and keys now that a GPIO driver exists.
The GPIO driver has also been enabled in the board defconfig, since it
is required to run some basic samples (e.g. blinky).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add GPIO driver for Gigadevice SoCs. The driver supports devices with
the AF and AFIO models.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
- The gpio dt-bindings were not included
- gpio-controller property was not present in gpio nodes
- number of gpio cells was not present in gpio nodes
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
- The gpio dt-bindings were not included
- gpio-controller property was not present in gpio nodes
- number of gpio cells was not present in gpio nodes
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add initial support for the GigaDevice External Interrupt Controller.
This driver is required to manage GPIO interrupts. Only EXTI lines 0 to
15 are supported for now (no LVD, RTC, etc.). Driver can be extended in
the future to add support for extra EXTI lines.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add DT node for EXTI (External Interrupt Controller). Only line
interrupts added for now (used for GPIO interrupts).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add DT node for EXTI (External Interrupt Controller). Only line
interrupts added for now (used for GPIO interrupts).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The nucleo_h743 allows extra capes to extend its functionality.
In our case it has been extended to use 32MiB SPI-NOR memory
connected to QUADSPI dedicated pins from block2.
Moreover, upper 16MiB of SPI-NOR memory has been used to store
littlefs data to test 4B addressing mode (which may cause problems
when NOR-flash is larger than 16 MiB).
Now the littlefs sample can be used to test this extension:
west build -p always -b nucleo_h743zi ./zephyr/samples/subsys/fs/littlefs
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This change provides support for 4 IO read (via 4READ command) and
program (via 4PP). Flash memory pins SIO[0123], CLK and CS are used.
All of them are controlled by stm32 QSPI IP block.
The instruction code for fast reading as well as number of latency
cycles required are read from SFDP structure provided by flash memory.
The number of required read latency cycles when performing reading
is the sum of SPI-NOR memory mode bits and wait states (also named
as 'dummy cycles').
It also has been assumed that memory, which supports fast read (4READ),
also will support fast programming (4PP command) as this information is
not available in SFDP.
One also need to enable the QUAD IO support in board's device tree by
defining 'spi-bus-width = <4>' property. It is required as it may
happen that not all QSPI dedicated pins are used (for example only two
of them are available).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
For proper operation of QUADSPI IP block, both sides of communication;
NOR flash memory and STM32 controller need to support 4 IO
transmission.
After this change the QSPI stm32 driver is able to program NOR flash
memory to switch itself to use all 4 IO lines (SIO[0123]) to transmit
and receive data.
The QE bit (in SPI-NOR's Status Register) is the non-volatile one, so
setting it is done only once (at first boot of the device).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This commit provides define for reading the control register (CR) on
the flash memory.
In that register the information about 4B addressing is stored.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
The spi-bus-width property provides information if the target system
has all SIO[0123] pins connected to NOR flash memory.
It must be equal to 4 to enable QSPI 4 IO operation.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Some flash memories connected to QUADSPI IP block on stm32[fh]7 devices
require proper reset pulse before configuration.
This patch adds two new properties - the 'reset-gpios' phandle,
which allows specifying GPIO pin for RESETn pulse and
'reset-gpios-duration', which provides the time (in ms) for reset
duration.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
