Commit graph

4 commits

Author SHA1 Message Date
Yong Cong Sin
e6dd68ec89 arch: riscv: introduce CONFIG_RISCV_GP_PURPOSE choice
Introduce `CONFIG_RISCV_GP_PURPOSE` choice to make sure that only
one of `CONFIG_RISCV_GP` or `CONFIG_RISCV_CURRENT_VIA_GP` can be
enabled, instead of relying of dependencies.

To do that, introduce a new
`CONFIG_RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING` that can be selected
by SoC when it implemented global pointer (GP) initialization for
relative addressing in its linker.

`CONFIG_RISCV_GP` will be the default choice when
`CONFIG_RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING=y`

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
2024-11-28 12:51:09 +01:00
Yong Cong Sin
4e54cff223 soc: qemu: riscv: update IRQ config
- Update `MAX_IRQ_PER_AGGREGATOR` to 1024 to match with the
  devicetree
- Update `2ND_LEVEL_INTERRUPT_BITS` to 11 bits to
  be able to encode the L2 IRQs.
- Update `NUM_IRQS` to 1036 (L1 has 12, L2 has 1024)

Update the `MAX_IRQ_PER_AGGREGATOR` config in testcase
accordingly, so that it won't overflow the configured bits.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
2024-09-06 14:06:23 -05:00
Marcio Ribeiro
cb583995b8 arch: riscv: imply XIP config pushed to SoC level
'imply XIP' pushed from arch/Kconfig/'config RISCV' to riscv SoCs Kconfig
files to allow riscv SoCs having XIP enabled (or not) at SoC level

Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
2024-08-31 06:47:52 -04:00
Jamie McCrae
f903052f42 soc: Move non-grouped qemu boards into qemu folder
For the 2 SoCs without a vendor, put them into a generic qemu
folder

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
2024-03-22 00:56:51 +01:00