None of the common DF configs should depend on using BT_LL_SW_SPLIT.
Added dependencies to it where this was the case.
Signed-off-by: Rubin Gerritsen <rubin.gerritsen@nordicsemi.no>
These configurations are tighlty coupled to the implementation,
so these should be hidden when not using BT_LL_SW_SPLIT.
Signed-off-by: Rubin Gerritsen <rubin.gerritsen@nordicsemi.no>
Some controllers may support only TXing or RXing CTE.
As all DF features are guarded by BT_CTLR_DF, we need to ensure
that it is possible to select those when only TX or RX is available.
Signed-off-by: Rubin Gerritsen <rubin.gerritsen@nordicsemi.no>
Move period and pulse computation to right before
the channel enable code.
That fixes the inability to disable the channel by
providing the period of 0.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
Add support for the fdcan peripheral to the stm32u5 series device tree
include. This can be applied here since (at present) all of the stm32u5
series MCUs have an FDCAN peripheral.
Signed-off-by: Peter Maxwell Warasila <madmaxwell@soundcomesout.com>
The STM32u% series of processors has a unique set of clock sources for
the FDCAN peripheral. This brings the selection in line with the
existing can_stm32fd clock selection Kconfigs.
This change was tested on a proprietary board using the STM32U5 series
which exposes the CAN pins of the SOC using a transciever on a live CAN
bus as well as on the nucleo_g474re board from ST in loopback mode.
HSE and PLL1Q tests run and all passed.
PLL2P is not currently supported by the clock drivers for STM32U5, and
as such is currently untested. When this support is added, the driver
should be able to use this clock without issue.
When changes from #42097 are merged this fix should be deprecated in
favor of using the methods outlined there.
Signed-off-by: Peter Maxwell Warasila <madmaxwell@soundcomesout.com>
Update the documentation to inform about /omit-if-no-ref/ when using the
node-based approach.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The file with pinctrl nodes has been updated to
st/g0/stm32g0b1r(b-c-e)tx-pinctrl.dtsi for this board.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
All DT nodes end up being part of the generated 'devicetree_unfixed.h'
header, wether they are referenced or not. The number of entries in that
file can grow quickly when using pre-generated pinctrl nodes.
Considering <devicetree.h> (file uncluding devicetree_unfixed.h) is used
in lots of places nowaday, not using /omit-if-no-ref/ can lead to
increased build times.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
When in_len is 0 then length is calculated from the package and
assignment was missing.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
With the new <zephyr/> include prefix, the "types" header ended up being
located in <zephyr/zephyr/types.h>, ie weird. Code that hasn't migrated
to <zephyr/zephyr/types.h> (no occurences in tree) will be automatically
prepared for the removal of the legacy include path. Most applications
will not be impacted as both include and include/zephyr are now in the
include path, and they'll be already prepared for the future.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
When legacy mode is enabled, Zephyr includes both include/ and
include/zephyr. Allow the zefi.py script to accept multiple include
paths to cover this scenario.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Allow mwdt toolchain usage for 2 cores HSDK configuration
as we have it for 4 cores configuration.
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Set the PCR[MUX] field to kPORT_MuxAsGpio as part of configuring a GPIO
pin. This removes the need to explicitly call pinmux_pin_set() in board
code.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
The OpenISA RV32M1 pinctrl groups need a dummy pinctrl node to populate
with pinctrl options at the board level.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Add OpenISA RV32M1 pinctrl header file to define SoC specific pinctrl_soc_t
structure. This is used to store pin configurations for the pinctrl driver.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
This adds lazy floating point context switching. On svc/irq entrance,
the VFP is disabled and a pointer to the exception stack frame is saved
away. If the esf pointer is still valid on exception exit, then no
other context used the VFP so the context is still valid and nothing
needs to be restored. If the esf pointer is NULL on exception exit,
then some other context used the VFP and the floating point context is
restored from the esf.
The undefined instruction handler is responsible for saving away the
floating point context if needed. If the handler is in the first
irq/svc context and the current thread uses the VFP, then the float
context needs to be saved. Also, if the handler is in a nested context
and the previous context was using the FVP, save the float context.
Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
This commit updates the Cortex-R reset routine to initialise
(synchronise) the VFP D16-D31 registers when Dual-redundant Core
Lock-step (DCLS) is enabled.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Grouping the FPU registers together will make adding FPU support for
Cortex-A/R easier later. It provides the ability to get the sizeof and
offsetof FPU registers easier.
Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
Cortex-A/R use a descending stack frame and the hardware does not help
with the stacking. This led to some less than desirable workarounds in
the exception code where the basic stack frame was saved twice.
Rearranging the order of the exception stack frame removes that problem
and provides a clearer path to saving CPU context in a fully descending
manner.
Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
When Dual-redundant Core Lock-step (DCLS) topology is used, the VFP
registers across the two redundant cores must be manually initialised
and synchronised, and this requires the `-mfloat-abi=hard` option to
be specified.
This commit forces the use of FP "hard" ABI on the VFP-equipped cores
that are configured in DCLS topology.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit updates the Zephyr build system to support specifying
advanced floating-point compilation options derived from the newly
introduced unified floating-point configurations.
The following changes are introduced by this commit:
1. Specify architecture floating-point option to the `-mcpu` flag.
2. Specify floating-point unit (FPU) type using the `-mfpu` flag.
Note that the `-march` flag is not specified separately because the
`-mcpu` flag provides more detailed architecture options and this
makes the `-march` flag redundant.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit adds the unified floating-point configuration symbols for
the ARM architectures.
These configuration symbols allow specification of the floating-point
coprocessors, such as VFP (also known as FP for Cortex-M) and NEON,
for the ARM architectures.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
For testing, assume that the Cortex-A/R platforms are using a GIC
interrupt controller. Use the last GIC SGI to trigger an interrupt for
the test.
Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
This commit adds the `mps3_an547` board, a Cortex-M55 platform, as an
integration platform for all CMSIS-DSP FPU test cases so that the
M-Profile Vector Extension (MVE) vector function implementations are
tested in the CI.
With this change the FPU-enabled test coverage is as follows:
* mps2_an521_remote (Cortex-M33) tests FPU/DSP-enabled scalar function
implementations.
* mps3_an547 (Cortex-M55) tests FPU/DSP-enabled MVE vector function
implementations.
This also has a side effect of comprehensively exercising the M-Profile
Vector Extension support in the ARM architecture port, thereby ensuring
the arch-level FPU/DSP/MVE support is not broken.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This reverts commit 96c7f6ab75.
Zephyr SDK 0.14.1 now includes QEMU 6.2, which supports the emulation
of the MVE instructions.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This reverts commit 91d4b7766c.
Zephyr SDK 0.14.1 now includes QEMU 6.2, which supports the emulation
of the MVE instructions.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit adds support for testing the vector implementation of the
FIR filter functions when the MVE is enabled.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit adds support for testing the vector implementation of the
Biquad filter functions when the MVE is enabled.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The MVE vector version of the statistics functions are slightly less
accurate than the scalar equivalents, so allow a higher relative error
threshold when the MVE is enabled.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The MVE vector version of the `vinverse` function is slightly less
accurate than the scalar version, so allow a higher relative error
threshold when the MVE is enabled.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit adds the missing common tables dependency for the SVM
functions.
The `exp_tab` and `exp_tab_f16` tables are required by the SVM
functions when the MVE is enabled.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
