Commit graph

63904 commits

Author SHA1 Message Date
Daniel DeGrasse
e74d8457c4 doc: storage: update storage documentation for SD subsystem
add section about SD subsystem to disk documentation, and document new
SDHC SPI bindings

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-04-29 14:21:36 -05:00
Daniel DeGrasse
8dc3d510b8 doc: peripherals: add documentation for SDHC peripheral
add documentation for SDHC peripheral driver.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-04-29 14:21:36 -05:00
Daniel DeGrasse
102f4c25f8 drivers: disk: remove legacy SDMMC SPI driver
remove existing SDMMC SPI driver, since it is replaced by the SPI mode
SD host controller driver.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-04-29 14:21:36 -05:00
Daniel DeGrasse
cb34ae41da boards: use zephyr,sdhc-spi-slot over zephyr,mmc-spi-slot
switch all in tree usage of zephyr,mmc-spi-slot to zephyr,sdhc-spi-slot.
This will change all boards to use the new SD subsystem instead of the
SDMMC SPI driver

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-04-29 14:21:36 -05:00
Daniel DeGrasse
c91d473ead drivers: imx_usdhc: change DT_COMPAT string to imx-usdhc
with the legacy USDHC driver fully removed from the tree, the
nxp,imx-usdhc binding can now be used for the new SD host controller
driver.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-04-29 14:21:36 -05:00
Daniel DeGrasse
409cc23022 drivers: disk: remove legacy nxp USDHC driver
all in tree SOCs with the USDHC peripheral have now been converted to
use the new SD host controller USDHC driver, so remove legacy NXP disk
USDHC driver.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-04-29 14:21:36 -05:00
Daniel DeGrasse
2fbfed9804 soc: imx_rt: added support for nxp imx_usdhc SDHC driver to RT600/500
added support for NXP iMX RT600/RT500 to use to SDHC driver, with SD
subsystem. Tested with RT685 EVK

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-04-29 14:21:36 -05:00
Daniel DeGrasse
d108b6417f boards: lpcxpresso55s69_cpu0: enable spi mode SD card.
Enable SD card running in SPI mode, using the SD subsystem.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-04-29 14:21:36 -05:00
Daniel DeGrasse
a3182ced7a drivers: sdhc: add SD SPI mode host controller driver
Add SDHC driver implementing spi mode support for SD cards. This driver
implements the standard SD host controller APIs, and sets the host
property "is_spi" to indicate to the SD subsystem the card will be
running in SPI mode.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-04-29 14:21:36 -05:00
Daniel DeGrasse
a18338bf45 soc: rt11xx: Enable USDHC SD host controller on RT1170
Enable SD host controller driver for RT1170, so the EVK can use the new
SD subsystem.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-04-29 14:21:36 -05:00
Daniel DeGrasse
aef290bb4d boards: Enable USDHC driver for all RT10xx based boards
Enable new USDHC driver for all RT10xx boards, since those will have
the SDHC driver selected by Kconfig

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-04-29 14:21:36 -05:00
Daniel DeGrasse
a79f485487 drivers: disk: add SDMMC zephyr disk driver
Add generic sdmmc zephyr disk driver, which uses the SDMMC subsystem

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-04-29 14:21:36 -05:00
Daniel DeGrasse
aadcc97c68 tests: subsys: sd: Add SDMMC subsystem test
Add SDMMC subsystem test, to verify functionality of SDMMC portion of
subsystem.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-04-29 14:21:36 -05:00
Daniel DeGrasse
64c5b93d5c sd: Add sdmmc protocol stack
Add SDMMC driver to subsystem. SDMMC driver will handle initialization,
as well as SDMMC I/O. SD mode support is currently supported, SPI mode
support is not.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-04-29 14:21:36 -05:00
Daniel DeGrasse
3e8bbee9ed sd: Add common SD initialization code
All SD cards require SD CMD0 (reset) and CMD8 (send IF cond) at boot.
Add this portion of the initialization flow to SD subsystem, as well as
query command to check if card is SDIO.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-04-29 14:21:36 -05:00
Daniel DeGrasse
d90a16f591 include: sd: Add SD subsystem header files
Add SD subsystem headers. SD subsystem contains generic header for SD
initialization, and headers for SDIO and SDMMC cards.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-04-29 14:21:36 -05:00
Daniel DeGrasse
5b5e01bc69 tests: sdhc: Add SD host controller driver test
SD host controller driver runs basic SD host controller tests, including
checking SD presence, and sending commands to SD card. No data transfer
is performed.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-04-29 14:21:36 -05:00
Daniel DeGrasse
32cd207f95 boards: mimxrt1064: Enabled new SDHC driver
Enabled new SDHC driver for mimxrt1064 evk

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-04-29 14:21:36 -05:00
Daniel DeGrasse
792cae9f7d dts: sdhc: Add SDHC DTS bindings
Add generic SDHC dts binding, as well as DTS binding for NXP USDHC.
Update iMX.RT DTS binding to use USDHC compatible

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-04-29 14:21:36 -05:00
Daniel DeGrasse
6aaa2b5d33 drivers: sdhc: Implement NXP USDHC SDHC driver
Implement SDHC driver for NXP USDHC peripheral, supporting all api calls
available in the sdhc driver. This implementation leverages NXP's HAL,
and simply implements a shim layer over the HAL itself.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-04-29 14:21:36 -05:00
Daniel DeGrasse
3f3a59377d drivers: sdhc: Add SD host controller driver API
Add api for SD host controller driver. SD host controller driver
supports the following operations:

- reset: reset host controller state
- request: send SD command and data via SDHC
- set_io: set I/O settings (voltage, clocks, etc..) on SDHC
- get_card_present: check for card presence
- execute_tuning: run tuning process for UHS cards
- card_busy: check if SD card bus is busy
- get_host_props: get host controller properties

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-04-29 14:21:36 -05:00
Daniel DeGrasse
c8041e87c9 include: sd: Add SD specification definition
SD specification definition required for SD host controller headers.
Add header file with SD specification definitions.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-04-29 14:21:36 -05:00
Daniel DeGrasse
aeb06640d3 MAINTAINERS: Make myself the disk subsystem maintainer
Add myself as the disk subsystem maintainer, and move jfischer-no to
be a collaborator

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-04-29 11:24:35 -04:00
Maciej Perkowski
bf3cd116e9 samples: tmf: psa: Increase timeout for psa_protected_storage_test
The test takes longer and requires its timeout to be increased
as in this commit.

Signed-off-by: Maciej Perkowski <Maciej.Perkowski@nordicsemi.no>
2022-04-29 16:22:32 +02:00
Michal Sieron
5098aaa2d1 hwinfo: hwinfo_litex: Make compatible with both 8 and 32-bit CSRs
LiteX CSRs can only be accessed on addresses aligned to 4 bytes.
That's why in 32-bit CSRs case there is bit shifting needed.

Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
2022-04-29 16:11:53 +02:00
Michal Sieron
2485c0232b pwm: pwm_litex: Use LiteX HAL
Removed register sizes from config struct, as they are known.
This allowed to remove driver specific function reading from CSR and use
`litex_write*` functions from LiteX HAL.

Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
2022-04-29 16:11:53 +02:00
Michal Sieron
0bfa223c68 entropy: entropy_litex: Use LiteX HAL
Use `litex_read` instead of separate implementation in driver.

Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
2022-04-29 16:11:53 +02:00
Michal Sieron
34a4b2b916 serial: uart_liteuart: Use LiteX HAL
Use LiteX HAL functions instead of `sys_read*` or `sys_write*`
functions.
They use them inside, but choose which one to use according to
configured CSR data width.

Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
2022-04-29 16:11:53 +02:00
Michal Sieron
e3db9a49c8 ethernet: eth_liteeth: Avoid bitwise operations
With universal LiteX HAL working, there is no need to perform multibyte
reads and writes using bitwise operations.
Just use appropriate `litex_read*` or `litex_write*` function.

Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
2022-04-29 16:11:53 +02:00
Michal Sieron
0c738b7f79 ethernet: eth_liteeth: Use LiteX HAL
Use LiteX HAL functions instead of `sys_read*` or `sys_write*`
functions.
They use them inside, but choose which one to use according to
configured CSR data width.

Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
2022-04-29 16:11:53 +02:00
Michal Sieron
b9c836b70a timer: litex_timer: Use LiteX HAL
Use LiteX HAL functions instead of `sys_read*` or `sys_write*`
functions.
They use them inside, but choose which one to use according to
configured CSR data width.

Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
2022-04-29 16:11:53 +02:00
Michal Sieron
2e9154a418 soc: litex-vexriscv: Rewrite litex_read/write
Changes signature so it takes uint32_t instead of pointer to a
register.
Later `sys_read*` and `sys_write*` functions are used, which cast
given address to volatile pointer anyway.

This required changing types of some fields in LiteX GPIO driver and
removal of two casts in clock control driver.

There was a weird assert from LiteX GPIO driver, which checked whether
size of first register in dts was a multiple of 4.
It didn't make much sense, so I removed it.

Previous dts was describing size of a register in terms of subregisters
used. New one uses size of register, so right now it is almost always
4 bytes.

Most drivers don't read register size from dts anyway, so only changes
had to be made in GPIO and clock control drivers.

Both use `litex_read` and `litex_write` to operate on `n`bytes.
Now GPIO driver calculates this `n` value in compile time from given
number of pins and stores it in `reg_size` field of config struct like
before.

Registe sizes in clock control driver are hardcoded, because they are
tied to LiteX wrapper anyway.

This makes it possible to have code, independent of CSR data width.

Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
2022-04-29 16:11:53 +02:00
Michal Sieron
f1e0cb6cb3 soc: litex-vexriscv: Implement universal LiteX HAL
Adds LITEX_CSR_DATA_WIDTH option to Kconfig
Depending on its value appropriate read/write handling is used
for accessing CSR registers.
By using `>=` in preprocessor conditions it is somewhat future-proofed.

Doesn't touch `litex_read` and `litex_write` yet.

Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
2022-04-29 16:11:53 +02:00
Yuriy Vynnychek
e71448a00d shell: fix missing "update" for the last RXRDY signal
Fixed the issue when sometimes "update" is not called for the
last RXRDY signal. First, need to reset the signal and only
after that need to call the "update" function.

Signed-off-by: Yuriy Vynnychek <yura.vynnychek@telink-semi.com>
2022-04-29 16:11:43 +02:00
Benedikt Schmidt
86469b1d0b drivers: clock_control: Make LSE driving configurable
Make the LSE driving capability configurable for the STM32 series.
Fixes #44737.

Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
2022-04-29 16:11:34 +02:00
Georgij Cernysiov
0d44525eb7 dts: arm: st: h7: stm32h750: add flash config
Adds write and erase block size configuration.

Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
2022-04-29 16:11:04 +02:00
Yong Cong Sin
9f14cf8a21 dts: arm: stm32g0b1: Add support for die temp sensor
Add node for the die temp sensor with configurations from
the datasheet.

Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
2022-04-29 16:10:51 +02:00
Yong Cong Sin
fbd0cd01d5 drivers: sensor: stm32_temp: setup channel before adc_read
Currently the driver only setup the ADC to read from the
internal temperature channel on init. However, it is possible
that some other application that uses the ADC can setup the
ADC to read from some other channel and therefore subsequent
stm32_temp_sample_fetch will fail to read the targeted channel.

Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
2022-04-29 16:10:51 +02:00
Yong Cong Sin
94624dc0c5 drivers: sensor: stm32_temp: No need to calibrate ADC
The ADC should be calibrated on init, there is no requirement
to calibrate ADC again on stm32_temp_init, remove it.

Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
2022-04-29 16:10:51 +02:00
Veijo Pesonen
d8b7449b52 net: lwm2m: SenML CBOR key ordering
Keys' order - bn, n - might differ from the default due to
Length-First Map Key Ordering rules.

Signed-off-by: Veijo Pesonen <veijo.pesonen@nordicsemi.no>
2022-04-29 16:10:43 +02:00
Veijo Pesonen
975d170792 net: lwm2m: use stack for SenML CBOR data
Formatter data are is shared between different threads.

Signed-off-by: Veijo Pesonen <veijo.pesonen@nordicsemi.no>
2022-04-29 16:10:43 +02:00
Veijo Pesonen
a1bd90646e net: lwm2m: adds README
Includes instructions for generating the SenML CBOR encoder and
decoder.

Signed-off-by: Veijo Pesonen <veijo.pesonen@nordicsemi.no>
2022-04-29 16:10:43 +02:00
Veijo Pesonen
98b22a1850 net: lwm2m: SenML CBOR optimisations
Regenerates the encoder and decoder. Treats integers and floating-point
values as separate entities instead of saying that those are numerical
values. Brings some memory savings.

Signed-off-by: Veijo Pesonen <veijo.pesonen@nordicsemi.no>
2022-04-29 16:10:43 +02:00
Veijo Pesonen
b78dd2498a net: lwm2m: Sets ct to registration msg
Tells the server which content format is preferred in a registration
message.

Signed-off-by: Veijo Pesonen <veijo.pesonen@nordicsemi.no>
2022-04-29 16:10:43 +02:00
Veijo Pesonen
4f76b194a4 net: lwm2m: empty CBOR array support
Makes possible to write an empty CBOR array if there are no SenML CBOR
records that needs to be written. This came up when trying to delete a
portfolio object instance.

Signed-off-by: Veijo Pesonen <veijo.pesonen@nordicsemi.no>
2022-04-29 16:10:43 +02:00
Veijo Pesonen
aa42e3e238 net: lwm2m: enable SenML CBOR
With LwM2M v1.1 SenML CBOR is preferred over SenML JSON.

TLV is on by default only with v1.0.

Signed-off-by: Veijo Pesonen <veijo.pesonen@nordicsemi.no>
2022-04-29 16:10:43 +02:00
Veijo Pesonen
60eaafe293 net: lwm2m: SenML CBOR gencode adaption
Generated code needs some modifications for it to work correctly.

Adds license information.

Signed-off-by: Veijo Pesonen <veijo.pesonen@nordicsemi.no>
2022-04-29 16:10:43 +02:00
Veijo Pesonen
0562de9fbe net: lwm2m: SenML CBOR RW support
* LwM2M v1.1 SenML CBOR content format support.
* Composite operations
* SEND functionality

Signed-off-by: Veijo Pesonen <veijo.pesonen@nordicsemi.no>
2022-04-29 16:10:43 +02:00
Lingao Meng
2ef96e2f66 Bluetooth: Host: Fix unable cleanup conn
The peripheral is configured to update the connection
parameters for 5 seconds by default.

There is an abnormal situation with a very low probability.

The central actively disconnects or abnormally disconnects the
Bluetooth connection at the same time.

At this time, the connection disconnection event will be
handled by BT RX.

At this time, sysworkq has sent a parameter update request and
will receive a reply with status = 0x02, because the handle is
invalid at this time.

We can not just cancel work, because work->flag may be
in K_WORK_RUNNING, so work->flag is set to K_WORK_CANCELING
and subsequent conn_cleanup will unable call k_work_rescheduler
successfully.

According submit_to_queue_locked will return ret = -EBUSY.

	if (flag_test(&work->flags, K_WORK_CANCELING_BIT)) {
		/* Disallowed */
		ret = -EBUSY;
As a result, the connection cannot be cleanup correctly.

Signed-off-by: Lingao Meng <menglingao@xiaomi.com>
2022-04-29 15:35:10 +02:00
Adrien Rouault
bc47f66062 drivers: lora: sx127x: fix missing reset gpio instantiation
Instantiate the value of `sx127x` reset GPIO

Signed-off-by: Adrien Rouault <adrien.rouault@nemeus.fr>
2022-04-29 15:30:10 +02:00