All of these should be no-ops for the following reasons:
1. User threads cannot configure memory domains, only supervisor
threads.
2. The scope of memory domains is user thread memory access,
supervisor threads can access the entire memory map.
Hence it's never required to reprogram the MPU on the current CPU
when a memory domain API is called.
This does not address the issue #27785 if a user thread in the domain
is running on some other CPU.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
All of these should be no-ops for the following reasons:
1. User threads cannot configure memory domains, only supervisor
threads.
2. The scope of memory domains is user thread memory access,
supervisor threads can access the entire memory map.
Hence it's never required to reprogram the MPU when a memory domain
API is called.
Fixes a problem where an assertion would fail if a supervisor thread
added a partition and then immediately removes it, and possibly
other problems.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We make a policy change here: all threads are members of a
memory domain, never NULL. We introduce a default memory domain
for threads that haven't been assigned to or inherited another one.
Primary motivation for this change is better MMU support, as
one common configuration will be to maintain page tables at
the memory domain level.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We don't have use-cases and it introduces complexities with
allocating page tables on MMU systems.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
LVGL objects have been alphabetically sorted. The aim of this change is
to help locating objects as well as keeping track of them.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
LVGL Kconfig settings have been splitted into more granular units in
order to improve readability and maintenance.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Align all Kconfig option names with LVGL names. The followed rule:
LV_(.*) -> CONFIG_LVGL_(.*).
Also replaced LVGL boolean configuration entries using if/else/endif
with direct IS_ENABLED macro.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Fixes: #27237
This commit fixes an issue when `zephyr_module.py` was executed outside
a west workspace.
This would happen when build an out-of-tree (out-of-workspace)
application, in which case the current west workspace would be unknown.
This is now changed, so that execution of `zephyr_module.py` will be
done in the current Zephyr base.
This ensures that the west workspace that holds the current Zephyr will
be the same workspace used for west list, and hence solve fix the issue.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
This commit adds the LiteX I2S devices usage example with:
- i2s rx and tx initialization,
- i2s rx and tx configuration,
- i2s rx receiving,
- i2s tx sending.
An application is a simple sound loopback - it allows to connect
a music source and a receiver such as headseat and listen to it.
Signed-off-by: Pawel Sagan <psagan@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
This removes a cast when getting the isr eth address from the isr table.
Signed-off-by: Pawel Sagan <psagan@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
* add toolchain abstraction for coverage
* add select HAS_COVERAGE_SUPPORT to kconfig
* port gcov linker code to CKake for arc
Signed-off-by: Jingru Wang <jingru@synopsys.com>
Make the flash-backed USB mass storage sample depend on usb_device and
flash instead of just flash.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Add support for running the JEDEC SPI NOR flash sample on the ARM
Cortex-M1 DesignStart FPGA reference implementation.
Special care is needed to avoid overwriting part of the FPGA
configuration bitstream, which is stored in the onboard QSPI flash.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Add support for running the SPI loopback driver test on the ARM
Cortex-M1 DesignStart FPGA reference design.
Since Xilinx AXI Quad SPI IP only supports loopback mode when configured
for single line SPI width, we utilise the (normally disabled) single SPI
instance going to the optional V2C DAPLINK shield SD card slot for
testing purposes.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Add the Xilinx AXI Quad SPI IP instances present in the ARM Cortex-M1
DesignStart FPGA reference design and enable the instance connected to
the onboard SPI NOR flash containing the FPGA configuration bitstream.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Add SPI driver for the Xilinx AXI Quad SPI IP. Despite the name, this IP
block supports both single, dual, and quad line widths.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
The PA sync is now "deleted" (i.e. flags reset) before
the terminated callback is called, so that is
possible to create PA sync in the callback. One flag
was already cleared before for this reason, but one
other flag is also required, so we just clear
everything now.
Signed-off-by: Emil Gydesen <emil_gydesen@bose.com>
Removed the check for explicit scanning, such that
an application may create a PA sync while explicitely
scanning.
Signed-off-by: Emil Gydesen <emil_gydesen@bose.com>
In 'struct coap_resource' path description:
- the plus symbol represents a single-level wild card in the path;
- the hash symbol represents the multi-level wild card in the path.
This change keeps compatibility with RFC 7252 but allows handling
multiple requests in single function.
Signed-off-by: Eug Krashtan <eug.krashtan@gmail.com>
The EEPROM API, which was introduced in Zephyr v2.1.0 and has not seen
any changes since, has multiple implementations supporting a wide
variety of EEPROM backends (SPI, I2C, on-chip, simulator).
Bump the EEPROM API from "experimental" to "unstable" according to the
Zephyr API lifecycle process.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Most if not all drivers use an internal function
spi_context_configured() to bypass reconfiguring the SPI peripheral
when nothing has changed. That function determines change based on
comparing the struct spi_config pointer that was last used. This does
not work if a user changes fields within the pointed-to structure.
Document that pointer comparison may be used to detect changes.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Several of the values passed to the conversion failure diagnostic are
unsigned and/or 32-bit values, while all format specifiers are for
signed 64-bit integers. Make the specifiers consistent with the
argument.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
For the moment, we validate the flags on all RAM pages,
ensure that NULL is never mapped, and show that dumping
page tables doesn't crash.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We added support for 32-bit page tables, without PAE.
Add a build target to ensure it doesn't bit-rot.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Ancient 2-level IA32 page tables don't support "eXecute Disable".
Skip the test scenarios for them.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The x86 paging code has been rewritten to support another paging mode
and non-identity virtual mappings.
- Paging code now uses an array of paging level characteristics and
walks tables using for loops. This is opposed to having different
functions for every paging level and lots of #ifdefs. The code is
now more concise and adding new paging modes should be trivial.
- We now support 32-bit, PAE, and IA-32e page tables.
- The page tables created by gen_mmu.py are now installed at early
boot. There are no longer separate "flat" page tables. These tables
are mutable at any time.
- The x86_mmu code now has a private header. Many definitions that did
not need to be in public scope have been moved out of mmustructs.h
and either placed in the C file or in the private header.
- Improvements to dumping page table information, with the physical
mapping and flags all shown
- arch_mem_map() implemented
- x86 userspace/memory domain code ported to use the new
infrastructure.
- add logic for physical -> virtual instruction pointer transition,
including cleaning up identity mappings after this takes place.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The address was being truncated because we were using
32-bit registers. CONFIG_MMU is always enabled on 64-bit,
remove the #ifdef.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
