Comparator will monitor signal though ADC channel, based on
user configuration, callback will be triggered.
This will enable comparator functionality for nuvoton MCU utilizing its
ADC threshold detection feature. Implementation is exported through
sensor trigger API. Use of CONFIG_ADC_CMP_NPCX is required.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Align all sensor drivers that are using stmemsc (STdC) HAL i/f
to new APIs of stmemsc v2.01.
Requires https://github.com/zephyrproject-rtos/hal_st/pull/9
(merged as 52a522ca4a8a9ec1e9bb5bb514e1ab6f102863fe)
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Refactor code so that an unused variable 'adc' warning
is not generated when building for CONFIG_SOC_SERIES_STM32G4X
and not using adc1 or adc5.
Signed-off-by: Sam Hurst <sbh1187@gmail.com>
Bluetooth Host calculated authentication value correctly only
for data smaller than 255 bytes. If data is larger then
authentication transformation used wrong flags.
Since the issue was symmetric two Zephyr
based devices were able to understand each other. Hence,
other devices like Android or IOS smartphones weren't able
to authenticate large frames and broke communication.
Signed-off-by: Aleksandr Khromykh <aleksandr.khromykh@nordicsemi.no>
We want to use a sparse address space to identify invalid conversions
between cached and uncached address aliases. This patch adds a
__sparse_cache sparse annotation for that. Where those conversions
must be done that has to be supported by using the __sparse_force
sparse attribute. To avoid compiler complains about unknown
attributes we add a -Wno-attributes flag when building with sparse
support.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Refactor the Bosch M_CAN shared driver functions to get rid of the
front-end driver wrapper functions.
This requires flipping the relationship between shared config/data
structs and front-end config/data structs. Front-end drivers can now
store a pointer to their custom config/data structs in the .custom
fields of the can_mcan_config and can_mcan_data data structures.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Rename the private header file for the Bosch M_CAN shared driver code
from can_mcan_int.h to can_mcan_priv.h to follow the common naming
scheme.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Enable the messaging unit for NXP i.MX8M Mini EVK boards. This is a
necessary requirement to be able to run rpmsg examples later.
Signed-off-by: Matthias Fend <matthias.fend@emfend.at>
enable pinctrl for mimxrt685_evk. The pinmux file is retained to handle
setting up shared signal sets for I2S tests, since this pin mux setting
is not managed by the pin control driver.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
update help text for mcux rt pinctrl peripheral driver, to clarify it
does not support RT600/RT500 parts and only RT1xxx series parts.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
add support for setting pinmux when using IOPCTL peripheral, as well as
setting pin configuration properties.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
add pincontrol headers for IOCON peripheral present on NXP iMX RT600
and RT500 SOCs, and update LPC pin control driver for iMX RT family
differences.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This modification is required to enable flash encryption.
Using hal implementation of spi_flash calls maintains
compability amongs different socs while offering
latest esp-idf enhancements.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The original design intent with arch_sched_ipi() was that
interprocessor interrupts were fast and easily sent, so to reduce
latency the scheduler should notify other CPUs synchronously when
scheduler state changes.
This tends to result in "storms" of IPIs in some use cases, though.
For example, SOF will enumerate over all cores doing a k_sem_give() to
notify a worker thread pinned to each, each call causing a separate
IPI. Add to that the fact that unlike x86's IO-APIC, the intel_adsp
architecture has targeted/non-broadcast IPIs that need to be repeated
for each core, and suddenly we have an O(N^2) scaling problem in the
number of CPUs.
Instead, batch the "pending" IPIs and send them only at known
scheduling points (end-of-interrupt and swap). This semantically
matches the locations where application code will "expect" to see
other threads run, so arguably is a better choice anyway.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The work queue has a semi/non-standard reschedule point implemented
using k_yield(), with a check to see if the current thread is
preemptible. Just call z_reschedule_unlocked(), it has this check
internally and is the intended API for this.
Really, this is only a half fix. Ideally the schedule point and the
lock release should be atomic[1] via the more idiomatic
z_reschedule(). But that would take some surgery, so let's go with
the simpler cleanup first.
This also avoids having to duplicate logic that gets added to
reschedule points by an upcoming patch.
[1] So that they represent a condition variable and don't race at the
end. In this case the race is present but benign, since the only thing
we really want to know is that the queue thread gets a chance to run.
The only cost is an occasional duplicated/needless context switch if
two threads are racing on a submit.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
add pin control nodes for LPC SOCs, to be filled with pin control
settings at the board level.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Includes the definition of the STM32_DMA_STREAM_OFFSET
depending on the peripheral to adjust the first DMA channel
in the list of streams.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This defines the constant for the STM32_DMA_STREAM_OFFSET
to be 0 or 1 when counting the first DMA channel
depending on the stm32 soc and DMA peripheral version.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This complements the Kconfig possibility, and allows setting an
interface as default on runtime. Changing the default interface also
works around limitations when trying to use an offloaded interface
together with a native one.
Signed-off-by: Ole Morten Haaland <omh@icsys.no>
User switch on mimxrt series boards requires a pull up resistor
to ensure the GPIO state does not float
Fixes#45129
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
In the EC application, the system may jump between two built Zephyr
images when necessary. When jumping from the current image to the other,
the firmware switches the eSPI-related pins to GPIO function at
initialization if define alt1_no_lpc_espi in def-io-conf-list.
It causes the eSPI to reset and breaks the eSPI communication after the
image jump. This patch prevents it by removing alt1_no_lpc_espi from
def-io-conf-list.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
In the EC application, the system may jump between two built Zephyr
images when necessary. If we gate the eSPI clock at initialzation, it
will make the eSPI configuration which established by previous image
break and lost the communication between EC and host.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
The LPC platforms define memory in SRAM blocks that can be
combined to represent larger memory blocks to the CPU. Change
the cpu0 allocation to use SRAM0-SRAM2 for 192K and change
cpu1 to use SRAM3-SRAM4 for 80K.
Signed-off-by: David Leach <david.leach@nxp.com>
The LPC platforms define memory in SRAM blocks that can be
combined to represent larger memory blocks to the CPU. Change
the M4 allocation to use SRAM0+SRAM1 for 128K.
Signed-off-by: David Leach <david.leach@nxp.com>
LPC platforms define multiple SRAM memory blocks that are contiguous
in memory but the zephyr build system doesn't have a method to
specify all the nodes to be used for a CPU's chosen "zephyr,sram"
node. To be able to get full use of memory, sram0 is redefined to
80KB in size.
Fixes#43872
Signed-off-by: David Leach <david.leach@nxp.com>
Adding a reference implementation of the Non-Volatile Memory module
needed to join any LoRaWAN network.
This NVM is based on the SETTINGS subsys to store all the required
key to join and communicate on a LoRaWAN network.
Without proper NVM, one may experience errors when using OTAA
to join the network, as the device may violate anti-replay
protection (depending on the version of LoRaWAN).
Signed-off-by: Giuliano Franchetto <giuliano.franchetto@intellinium.com>
