In i2s_stm32_isr, remove the errors from SR register
i2s_stm32_configure, enable the rx path for H7 I2S compatible IP
Signed-off-by: Franck Thebault <franck.thebault@st.com>
Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
This commit should add all the functionality needed for the DMA
driver to work when PM is enabled.
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
Update the Quectel LCX6G device driver to use the modem chat
runtime API to modify the dynamic pair chat script.
This change makes the driver safer and more readible by
ensuring safe modification of the members of the modem chat
structures.
Signed-off-by: Bjarki Arge Andreasen <bjarki@arge-andreasen.me>
1. Emit stop when not in the correct state and unsupported ibi type.
2. For IBI(MDB), ignore the callback when target not in the
device tree list.
Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
In release V3.3 new STM32Cube HAL ethernet API was added to STM32 ethernet
driver for STM32F4, STM32F7 and STM32H7 series. At the same time, the
legacy API was deprecated for these series.
I'm now fully removing the legacy API support for these series.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Updated function parameters from `const struct uart_stm32_config *config`
to `USART_TypeDef *usart`. This change reduces the level of pointer
indirection, which minimizes repeated dereferencing and helps reduce
the overall code size.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
This change reduces the level of pointer indirection, which minimizes
repeated dereferencing and helps reduce the overall code size.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Introduce a hidden Kconfig option named HAS_WDT_DISABLE_AT_BOOT and
allow users to enable WDT_DISABLE_AT_BOOT only when that hidden option
is selected by a watchdog driver, i.e. disabling at boot is supported.
Select this new hidden option for all existing watchdog drivers that
refer to WDT_DISABLE_AT_BOOT.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This commit removes unnecessary initialization of the local variable
where its value is guaranteed to be overwritten by subsequent operations.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Use a code spell-checking tool to scan and correct spelling errors in
the following files:
- clock_stm32_ll_common.c
- clock_stm32_ll_h5.c
- clock_stm32_ll_h7.c
- clock_stm32_ll_u5.c
- clock_stm32_ll_wba.c
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
net_pkt_alloc_buffer() deducts the free space from the requested number
of bytes.
As ppp_save_byte() calls net_pkt_alloc_buffer() when the packet has one
byte available still, this causes all but the first net_buf in the
packet to be of size CONFIG_NET_BUF_DATA_SIZE - 1.
Consequences:
- With CONFIG_NET_BUF_FIXED_DATA_SIZE enabled, one byte per net_buf
gets wasted.
- CONFIG_NET_BUF_DATA_SIZE has typically an even, likely even a power
of two value. Using exactly one byte less per buffer causes
operations that require aligned memory (e.g. DMA) to become
inefficient or to not work at all.
Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
Fix timing in SPI bitbang driver.
The issue occurs with CPHA=1 when the input data is changed immediately
after the clock shift on the last bit of the read.
Because we read the input bit after changing the clock, this bit
becomes invalid.
Instead of doing wait, clock-change, read. Do wait, read, clock-change.
Signed-off-by: Joakim Andersson <joerchan@gmail.com>
The controller may be unavailable to receive packets because it is busy
on processing something or have packets to send to host. Need to free the
SPI bus and wait some moment to try again.
Signed-off-by: Aaron Ye <aye@ambiq.com>
The BLE controller of some Ambiq Apollox Blue SOC may have issue to
report the expected supported features bitmask successfully, thought the
features are actually supportive. Need to correct them before going to
the host stack.
Signed-off-by: Aaron Ye <aye@ambiq.com>
This commit add the SPI-based HCI support for the Ambiq Apollo3 Blue
SOC (e.g. Apollo3 Blue Plus, Apollo3 Blue) support.
Also correct the dependency of necessary peripheral.
Signed-off-by: Aaron Ye <aye@ambiq.com>
Some Ambiq Apollox Blue SOC (e.g. Apollo3 Blue) uses internal designed
BLEIF module which is different from the general IOM module for SPI
transceiver. The called HAL API will also be independent. This driver is
implemented for the BLEIF module usage scenarios.
Signed-off-by: Aaron Ye <aye@ambiq.com>
Clock must be restored as soon as the SoC leaves standby.
Keep the logic inside the SoC instead of delegate it to the pm
subsystem.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
The RTC subsystem in espressif's SOCs, among other tasks
is responsible for clock selection for CPU and for low
power domain clocks such as RTC_SLOW and RTC_FAST.
This commit allows for proper clock source and rate
selection for CPU, using the espressif,riscv and
espressif,xtensa-lx6/7 bindings.
It also enables clock selection for RTC_FAST and RTC_SLOW,
that impacts some peripherals, such as rtc_timer.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Print the raw DLC when enqueuing a CAN frame for sending, not the
corresponding number of bytes.
Fixes: #73309
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Zerorise the CAN frame before filling in data to ensure all data bytes are
initialized.
Fixes: #73309
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Save the reference of the start index of the `_sw_isr_table`
to the config struct, so that the `local_irq` can be used as
offset directly.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Previously the multi-level irq lookup table is generated by
looping through the devicetree nodes using macros & Kconfig,
which is hard to read and flimsy.
This PR shifts the heavy lifting to devicetree & DT macros such
that an interrupt controller driver, which has its info in the
devicetree, can register itself directly with the multi-level
interrupt architecture, which is more straightforward.
The previous auto-generated look up table with macros is now
moved in a file of its own. A new compatibility Kconfig:
`CONFIG_LEGACY_MULTI_LEVEL_TABLE_GENERATION` is added and
enabled by default to compile the legacy look up table for
interrupt controller drivers that aren't updated to support the
new architecture yet.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
VPR cores CLIC supports vectored mode only. Select
`GEN_IRQ_VECTOR_TABLE` such that it can't be disabled.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Add HCI driver generic to NXP platforms.
Update west.yml to have ble support for rw61x
Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
Signed-off-by: Yassine El Aissaoui <yassine.elaissaoui@nxp.com>
If rx buffer allocation has to be deferred to rx_thread, we need to stop
isr reading from mailbox as otherwise rx_thread won't be able to process
other buffers.
Since CMAC2SYS irq is cleared before data is read from mailbox, in case
rx buffer allocation was deferred we also need to trigger irq manually
to make sure all pending data is processed.
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
- Add initial version of CYW920829M2EVK-02 board
- [drivers: clock_control] Make it possible to set up both iho and imo
clocks instead of just one or the other
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
The CMAC uses lp_clk as a sleep clock so it has to be updated if
frequency of lp_clk has changed. This happens either after XTAL32K
settling or RCX calibration.
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Note that the Init of the alarm has no need for BCD2BIN conversion,
the LL_RTC_ALMx_Init will do. Add more log debug
The driver must clear the ALARM enable bit before wrting the alarm
registers.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Set a Calendar using the LL functions LL_RTC_TIME_Init
and LL_RTC_DATE_Init. Add more DBG info
On the stm32F2 serie, check RS Flag after setting calendar registers.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Make it a little bit easier to read using already existent
definitions for the registers used here.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
When function sys_clock_set_timout() is called with small value
(i.e. 1) calculated time to be programmed to TIMER2 reload
register may be such that is expires before code set's it
up. In that case timer interrupt will be scheduled in far
future.
With this change, code checks after it sets reload value if
requested time already passed and if so TIMER2 interrupt
is marked as pending to avoid races.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
This driver implements a simple MBOX device which supports a single
instance, two channels (one for each direction), and only signalling
mode with no data transfer. Signalling to another core is achieved by
taking and giving two hardware semaphores, similar to the STM32 HSEM
IPM driver.
Signed-off-by: Celina Sophie Kalus <hello@celinakalus.de>
Check the return values of commands such as spi_nor_cmd_* and
spi_nor_wait_until_ready and ensure they are propagated back to the
caller on error.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
The commit removes unneeded check for enter_4byte_addr_exist in
the function, as the utility function is supposed to set the address
by parsing enter_4byte_addr parameter, while the enter_4byte_addr_exist
used to exist only for DTS entries that directly set enter-4byte-addr
parameters for a flash node.
The change also moves LOG_DBG reporting enter_4byte_addr before
it is processed, to allow logging what actually function will be working
with, before it does so.
The enter_4byte_addr_exist is removed as it is no longer used anywhere.
Setting of data->flag_access_32bit has been moved in the same code block
as call to the spi_nor_cmd_write, as it can be only consequence of
successful call to that function.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
Subghzspi instances cannot have any pinctrl configs. This causes a
failure of the power management suspend and resume operations for the
subghzspi instance because no "default" pinctrl is found.
Fix that by skipping the pinctrl parts on subghzspi instances.
At the same time fix a copy and paste in the suspend error message.
Fixes: b567a7db83
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Add new channel: `SENSOR_CHAN_POS_DXYZ`, so that it is
consistent with other 3-axis channels.
Updated pytest, `sensor_shell` & `fake_sensor` accordingly.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
