Add header file for flash configuration blocks
which is an image header consumed by the RW bootrom.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add the Kconfig options and use the aliased
addresses for the bootcode regions of the IMX7D
and IMX6SX SOCs to allow the Linux rproc
framework to load the irq-vectors into
the correct memory areas.
Activating this option might enlarge the bin
file if the zephyr,flash and rom_start chosen
region addresses are not matching.
It is up to the user to enable this feature
based on code location choices (OCRAM, DDR, TCM...).
Signed-off-by: Jérémy LOCHE - MAKEEN Energy <jlh@makeenenergy.com>
Add DT node entries to RW for DAC and ADC.
Support the SOC required initialization of the DAC and ADC on RW.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Mask for FLEXSPI clock divider was being used when setting the FLEXSPI
clock selector value. Correct this to use the mask for the selector
instead of the divider.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Currently, only DCD bootheader was supported to configure the SDRAM.
On IMX RT1170, XMCD can be used as an alternative boot header to DCD.
XMCD is more advanced than DCD and enhances SDRAM access speed.
This is benefit for SDRAM access application.
Signed-off-by: Trung Hieu Le <trunghieu.le@nxp.com>
iMXRT1042 SOC should be clocked at 528 MHz maximum. Correct the clock
setup to use the system PLL.
Fixes#70755
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Allow configuration of the system pll on the iMXRT10xx series parts, via
a fractional pll node under the CCM module.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The HAS_MCUX_CSI (as well as all the HAS_MCUX_XXX) config was obsolete
and has been replaced by the DT_HAS_NXP_IMX_CSI_ENABLED (i.e.
DT_HAS_XXX_ENABLED). Drop it as well as all the dependencies on it.
Signed-off-by: Phi Bang Nguyen <phibang.nguyen@nxp.com>
Used multiple places in the tree. The idea is to determine if this node
corresponds to a specific node (e.g: flexspi) so that specific
configurations can get done. Without the fix, the macro expansions were
defaulting to false.
Signed-off-by: Luis Ubieda <luisf@croxel.com>
For CPP application, such as samples/cpp/cpp_synchronization/, it will
report the following building errors:
...
zephyrproject/modules/hal/nxp/imx/devices/MCIMX7D/./MCIMX7D_M4.h:5101:51:
error: 'reinterpret_cast<CCM_Type*>(808976384)' is not a constant
expression
...
The error is caused by commit: 72312feead
" arch: arm: cortex_m: Use cmsis api instead of inline asm in arch_irq_*"
This patch will cause kernel.h includes cmsis_core.h which includes soc.h,
so that soc.h will be used by c++ code.
This patch make soc.h can be c++ compatible.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
The dependencies should be in a 'depends on' clause.
Also, 'depends on PTP_CLOCK' is redundant because this is
within 'if PTP_CLOCK' already.
Additionally, conditionally include the PTP header in the mac driver.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add code to clock and release reset signal for USBOTG controller on
RW6xx SOC when USB is enabled, and add KConfig selection to indicate to
build system which USB controller this SOC uses.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
We need to use correct SOC name when naming the Kconfig.defconfig*
files.
So we need the following changes:
- mimx8mp -> mimx8ml8
- mimx8mm -> imx8mm6
- mimx8mn -> mimx8mn6
- mimx8mq -> mimx8mq6
Then we also need to take care of qualifiers name. Standard notation
uses "_" instead of "."
e.g : Kconfig.defconfig.mimx8mp.a53 -> Kconfig.defconfig.mimx8ml8_a53
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
This commit enables pinctrl on i.MX8ULP. This includes:
1) Adding `pinctrl_soc.h` header file.
2) Adding DTS node for IOMUXC1, which is one of the
IPs responsible for managing the 8ULP pads.
3) Adding .dtsi with pin definitions. For now, only
the LPUART7 pads are added to this file because this
is going to be the only consummer for now.
4) Modifying the `pinctrl_imx.c` driver to work for 8ULP.
5) Enabling the `CONFIG_HAS_MCUX_IOMUXC`, which is a
dependency of `CONFIG_PINCTRL_IMX`.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
In preparation for adding AMP support for i.MX RT6xx family we need
to rename existing cm33 support files to more specific names.
e.g mimxrt685_evk.dts -> mimxrt685_evk_mimxrt685s_cm33.dts
This will allow us to later add support for Cadence DSP found on i.MX
RT6xx series.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
imxrt6xx are dual core devices featuring an ARM Cortex-M33
core and an Cadence Xtensa HIFI4 Audio DSP.
Currently only m33 core is supported. In order to support
the Cadence DSP we need first to do some code-reorganization
for m33.
We start by moving all cm33 related code to its own directory
and introduce the cpuclusters property in soc.yml file.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
LPFlexcomm is a MFD device hence select this Kconfig whenever
it is enabled.
Remove the selection from the individual driver Kconfig files.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Change, for audio DSP and M7 cores, SOC_<name> to match
the exact soc name.
Update the board files accordingly.
These configs are used in SOF and NXP_HAL, so change
sha for these modules.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Enable sleep mode on LPC55S69 (corresponding to zephyr's runtime idle
mode). Add DT description and power api implementations.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add SoC initialization to set the UART RDC permission in the early
phase, so that the it can be used by Zephyr on Cortex-A cores.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
The SOC name `imx8ulp` has been just a placeholder until
support for the SOC's ADSP (since this is the only core
that's supported in Zephyr) could be added to the NXP HAL.
Now that the support has been added, to make use of it, the
SOC name `imx8ulp` has to be changed to `mimx8ud7`. As such,
this commit does the following:
1) Introduces SOC part number configuration - needed
by some HAL headers.
2) Replaces all occurrences of `imx8ulp` (as the SOC
name) with `mimx8ud7`.
3) Enables `CONFIG_HAS_MCUX`.
4) Aligns all `CONFIG_SOC_` configurations with the
new SOC name.
5) Updates SOF hash. This is needed to fix build issues
caused by this name change. This is not done in a separate
commit to preserve bisectability.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
MEMC_MCUX_FLEXSPI depends on code relocation being enabled on parts that
XIP from the FlexSPI by default and requires a string describing the RAM
region to relocate code into. Add these Kconfigs to the RW SOC port.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The core clock of 8ULP's HIFI4 DSP runs at 475.2MHz. As such,
correct the value of `CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC` to
reflect this.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Dependencies of NXP_IMXRT_BOOT_HEADER were set incorrectly for the
RT11xx series part when building a dual core image. The boot header
should be enabled by default for the primary M7 core, and always
disabled when MCUBOOT is used or the M4 core is targeted
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Unlike the remainder of the RT10xx series, the RT1011 SOC requires that
the flash configuration block be placed at an offset of 0x400 bytes,
instead of the start of the flash.
Fixes#70090
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
With the transition to HWMv2, `CONFIG_CPU_HAS_DCACHE` is no
longer selected. This causes issues with Sound Open Firmware
since this configuration allows the usage of DCACHE-related
cache management operations. As such, to fix said issues,
select `CONFIG_CPU_HAS_DCACHE` on all NXP ADSP SOCs.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Not all SOC cores within the NXP iMX RT family support power
management (for example, the Fusion F1 DSP has no support). Do not
select HAS_PM at the SOC family level, and instead select it at the
series level where applicable
Fixes#69731
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
