In addition to Kconfig options (soon to be deprecated), allow
configuring the regulators using DT.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Allow CONFIG_NRF_APPROTECT_LOCK and
CONFIG_NRF_SECURE_APPROTECT_LOCK with TF-M with all the SOC's
that support TF-M.
Signed-off-by: Markus Lassila <markus.lassila@nordicsemi.no>
DMM shall be initialized as early as possible to allow drivers to
use it. For example, uart may need it early since it starts
RX during initilization in some configurations.
Making dmm_init() public and calling it in soc init function.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
When not using BT, users may want to enable the cpunet core. Until now,
this has been done at board level (so duplicating unnecessary code)
using CONFIG_BOARD_ENABLE_CPUNET. The board-level options were usually
enabled automatically for BT, however, this was unnecessary as BT driver
already takes care of the setup.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Getting the required alignment size for memory region node
and device node needs to be handled by a separate macro.
Otherwise alignment of single byte is reported for any region.
Add a test that checks for this particular issue.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
Fixes an issue whereby multiple boards would be grouped when using
a regex to group them, and adds missing nRF91 entries to the list
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
For SOCs that do not implement a custom `__reset` function,
select `INCLUDE_RESET_VECTOR` so that Zephyr provides a default
implementation that simply jumps to `__initialize`
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
cpuppr can only use slow peripherals and uses RAM3 as RAM so
it does not need to use DMM.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
DMM was enforcing cache line alignment all memory regions, including
those which were not cacheable. Fixing it by using memory attribute
from the device tree to determine if alignment needs to be applied.
Because of that memory usage was significantly increased because
even 1 byte buffers (e.g. for uart_poll_out) was consuming 32 bytes
(cache line size).
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
The implementation of formula, to calculate HFXO INTCAP code,
had a rounding error. That may lead so small deviation of HFXO
clock accuracy.
The IPS formula uses capacitance values in piko Fartd units.
That requires use of floating point data types. To avoid that
implementation of the formula uses femto Farats (1000 smaller unit).
In the former implementation conversion from femto Farad to piko Farad
was done just after reading of the desired capacitance from DTS.
To make sure the calculations are correct the change of unit must be
done at very end. Also rounding must be applied.
Also the formula was split and more comments were added to make the
implementation clear.
The commit fixes the implementation of the IPS formula.
Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
There were two errors in calculations of LFXO INTCAP code:
- The value provided by DTS files is internal desired capacitance.
The value from DTS has to be "encoded" before use in INTCAP
calculations formula. The formula for encoding is:
CAPACITANCE_CODE = (<desired_value> - 4pF) / 0.5
Subtract of 4 is related with lowest value in the allowed range.
Division by 0.5 is related with change to steps size.
In former code the subtration of 4pF was missing.
- The mid_val calcuation was wrong due offset_k left shift by 4.
It should be left shift by 3 to get total left shift of 9.
That matches the left shift of former part of the equation.
Final integer value was calculated by right shift 10, it should
be right shift 9. Then rounding was done by use of mod by (1 << 10)
It should be mod by (1 << 9) and compared with (1 << 8), that is
half of 0-512 range.
Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
Time it takes to "erase" one "page" of rram is too low.
Where getting timeouts.
"erase" of rram is done by writing all the words.
one "page" is 4096 bytes meaning 1024 32bit words.
worstcase time it takes to write one 32bit word from
0x00000000 to 0xffffffff is about 42us, giving 42ms
to write 1024 words.
Signed-off-by: Martin Tverdal <martin.tverdal@nordicsemi.no>
The nrfutil device v2.4.x now supports the recover operation. Configure
run once to ensure that domains are not unnecessarily erased.
Signed-off-by: Rafał Kuźnia <rafal.kuznia@nordicsemi.no>
Fixes#72673
Follow-up to #70977 and #71590
The CMake linker generator doesn't have an API equivalent to `PROVIDE`,
but the existing `zephyr_linker_symbol()` function should do just fine.
It still lets us set `z_arm_platform_init = SystemInit` and thus keep
the reduced ROM space.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
DMM stands for Device Memory Management and its role is to streamline
the process of allocating DMA buffer in correct memory region
and managing the data cache.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
Erase and reset must run only once during flashing.
This prevents a situation, where the next flashed image erases the
previous one.
Signed-off-by: Rafał Kuźnia <rafal.kuznia@nordicsemi.no>
A single trigger of the TASK_FREQ_CHANGE task might not be enough, so
trigger twice to make sure the frequency gets updated.
Signed-off-by: Karsten Koenig <karsten.koenig@nordicsemi.no>
Add devicetree nodes for the Reset Information registers on nRF54H20,
along with a new binding.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Remove dead code that cannot be enabled.
Kconfig prevents us from enabling PM_S2RAM on 53 because it is not
supported any more.
But we still have some dead code left over in soc.c, so we delete this
code.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Created `GEN_OFFSET_STRUCT` & `GEN_NAMED_OFFSET_STRUCT` that
works for `struct`, and remove the use of `z_arch_esf_t`
completely.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Select the newly introduced nrf54lx compatible kconfig
option.
This is common both for real HW and for simulated HW,
allowing SW to behave appropriately for both.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Configure CAN120 MCAN core registers as non-cachable to prevent D-Cache
from inhibiting volatile accesses to the CAN120 MCAN registers. Also
apply non-cachable attribute to the message ram region. Even though the
MCAN driver handles cache invalidation/flushing, MPU faults are still
triggered (to be investigated).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Namespaced the generated headers with `zephyr` to prevent
potential conflict with other headers.
Introduce a temporary Kconfig `LEGACY_GENERATED_INCLUDE_PATH`
that is enabled by default. This allows the developers to
continue the use of the old include paths for the time being
until it is deprecated and eventually removed. The Kconfig will
generate a build-time warning message, similar to the
`CONFIG_TIMER_RANDOM_GENERATOR`.
Updated the includes path of in-tree sources accordingly.
Most of the changes here are scripted, check the PR for more
info.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
The nRF54H20 EXMIF peripheral requires word accesses. Doing accesses of
byte or half-word sizes results in bus fault.
Signed-off-by: Rafał Kuźnia <rafal.kuznia@nordicsemi.no>
`SB_CONFIG_VPR_LAUNCHER` can now be used in building a VPR target,
to enable automatic building of image that will launch the VPR.
Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
Hardware-specific properties should stay in sync with the definitions
provided by MDK. Existing measures for this include:
* The `validate_base_addresses.c` file included in every build;
* The `nordic-nrf-ficr-nrf54h20.h` header generated from SVD.
If there's information that cannot be extracted from SVD, it may have to
be validated against C types. Add `validate_binding_headers.c` for this
purpose, which automagically includes all `dt-bindings` headers included
by DTS in a given build.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Commit 149df6b61b ("soc: nordic: nrf54h20: Disable USBHS core cache")
inadvertedly removed default MPU regions defined in arm_mpu_regions.c.
Without the SRAM_0 region defined all builds with asserts enabled result
in failed assertion even before the kernel inits. The failed assertion
is the very last step of arch_kernel_init() when MPU areas are marked
for dynamic regions. Because the failure occurs so early, the device
appears completely dead.
Fix the issue by bringing the default regions to nrf54h20 custom
regions file.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Add `CHECK_DT_REG()` entries for a few additional peripheral types:
BELLBOARD, CCM, GRTC, HSFLL, UICR, and VPR.
For peripheral instances outside of the Global Domain, such as DPPIC020,
use domain-specific defines like NRF_RADIOCORE_DPPIC020 when validating.
These are always defined by the MDK, while NRF_DPPIC020 isn't guaranteed
to exist in those cases. Revise existing macro checks accordingly.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
If no HSFLL needs trimming, then `trim_hsfll()` should be compiled out.
This makes it easier to reuse the rest of `soc.c` out of tree.
Furthermore, some HSFLL instances can be trimmed before booting Zephyr,
so the FICR client properties in the DT binding should not be required.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Configure USBHS core registers as non-cachable to prevent D-Cache from
inhibiting volatile accesses to the USBHS core registers.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
The nRF54H20 implements a variant of the SPI DW peripheral that
has slightly different register layout. Enable it in the defconfig.
Signed-off-by: Rafał Kuźnia <rafal.kuznia@nordicsemi.no>
Adds configuration that allows nRF53 and nRF91-based boards to be
flashed through west using sysbuild for multiple images with the
recover or erase options and prevent running those commands for
each image being flash, which would make the device unbootable.
Also defers reset whilst all images for the cores of these SoCs
are flashed.
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
