Commit graph

45 commits

Author SHA1 Message Date
Marcio Ribeiro
77c350c149 soc: esp32: virtual e-fuses support
Adds support for virtual e-fuses on esp32 socs

Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
2025-06-04 17:00:20 +02:00
Raffael Rostagno
588c2e66e9 soc: esp32c6: Fix sleep routine
PMU related functions need to be located in IRAM when sleep
process is triggered, as cache is disabled past a certain point
in the execution of the sleep process.

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
2025-05-30 16:34:48 +02:00
Lucas Tamborrino
232e2c5a3c drivers: uart: espressif: Add LP UART driver
Add LP UART driver for LP Core

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2025-04-11 13:34:17 +02:00
Sylvio Alves
ac0705d59b soc: espressif: update restart procedure
Use esp_restart call to guarantee and registered
shutdown handlers will be triggered before rebooting.
This guarantees that subsystems like Wi-Fi and BLE
will deinit correctly.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2025-04-05 11:02:13 +02:00
Sylvio Alves
9857f114f8 linker: esp32: move regi2c_ctrl to iram
This prevents boot lock up due to critical sections
calls during bootloader stage.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2025-04-03 00:03:56 +02:00
Raffael Rostagno
eb606a8e7d soc: esp32: Update IRQ config for shared allocator
Update IRQ handling related files to unify interrupt controller
between Xtensa and RISCV devices.

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2025-04-02 19:02:27 +02:00
Lucas Tamborrino
c6f84d0ba2 boards: espressif: esp32c6: Add LP Core board support
Add ULP Coprocessor board support for C6.
This requires a change in the board qualifier depending on the build
target.
Update esp32c6 overlay and configuration files to the proper name.

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2025-03-21 17:05:20 +01:00
Lucas Tamborrino
0b9e4e013a soc: espressif: esp32c6: Add LP Core
Add ULP Coprocessor support for ESP32C6.

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2025-03-21 17:05:20 +01:00
Sylvio Alves
f22de9733b soc: esp32: riscv: fix interrupt allocator
Current interrupt allocator is not taking into account
reserved areas. In case of esp32c6, Wi-Fi isn't properly
configured, causing instability or even non-functional feature.
This adds the reserved area ranges for all risc-v based SoC and
unify the slot finding based on interrupt source.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2025-03-06 08:35:29 +00:00
Sylvio Alves
b8c710d6c4 soc: espressif: fix chip revision reading
Make sure chip revision reading returns real value
for some especific chip revision, which is currently
failing.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2025-03-04 18:26:34 +00:00
Sylvio Alves
1903a8f415 soc: espressif: fix optimization flag boot fault
When DEBUG_OPTIMIZATION or NO_OPTIMIZATION is
enabled, efuse reading fails during bootloader start.
Move those calls into IRAM area so that reading when
cache is disabled works without any faults.

In HAL side, we need to use low level calls to read
CPU id instead of Zephyr's default one.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2025-02-26 07:41:31 +01:00
Sylvio Alves
3c1e11c003 linker: espressif: clean up mcuboot iram entries
As a result of flash initialization improvements
and fixes, some of the mcuboot linker entries
are no longer necessary.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2025-02-14 17:07:40 +01:00
Sylvio Alves
69a6736ba1 soc: espressif: use commom board runner among chips
Currently, each SoC has its own CMakeLists.txt file
to handle esp32 runner.
This PR merged it all in a common file and fixes
missing configuration such as flashing frequency,
mode and size.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2025-02-14 17:07:40 +01:00
Sylvio Alves
36705c4f8e soc: espressif: remove vddio boost during boot
Removes the VDDSDIO control during boot for some SoCs.
Only ESP32 allows managing such configuration during
initialization.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2025-02-14 17:07:40 +01:00
Sylvio Alves
e36d702acd soc: espressif: move code start prior hw init
Make sure vector table and BSS clean up
is performed pior hardware initialization.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2025-02-14 17:07:40 +01:00
Sylvio Alves
10860ecbba soc: espressif: enable Wi-Fi/Bluetooth SW coexistence mgmt
Update and enable Wi-Fi/Bluetooth software coexistence management.
This improves package handling and is recommended to be used
in high traffic scenarios.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2025-02-12 20:20:11 +01:00
Jamie McCrae
a0d62db81f soc: espressif: Move MAIN_STACK_SIZE to defconfig files
Moves this Kconfig value to be the default in the
Kconfig.defconfig files

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
2025-02-11 10:12:23 +01:00
Marek Matej
6e6ab2f8ab soc: espressif: Remove ESP heap and use heap adapter
Remove ESP heap from the sources. System heap is default heap.
Use heap adapter layer to configure used heap.
Use MEM_POOL memory request config to Wi-Fi and Bluetooth drivers.
Update the Wi-Fi and BLE memory needs.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2025-02-05 17:49:54 +01:00
Marcio Ribeiro
c3b53d0fa3 soc: esp32xx: makes esp_console_init() calling conditional
Makes the esp_console_init() calling during hardware initialization
conditioned to CONFIG_ESP_CONSOLE

Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
2025-01-30 16:21:13 +01:00
Marek Matej
d276cf753f soc: espressif: Extend the program header
Add new fields to the `esp_image_load_header_t`

* provide IROM and DROM fields to fix debugging features
* extend the header to up to 96 Bytes for future use

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2025-01-14 00:01:20 +01:00
Sylvio Alves
5d05e28fce soc: espressif: keep RTC data after deep-sleep
This PR includes changes in all Espressif's SoCs to enable
keeping data in RTC memory after deep-sleep.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2025-01-10 18:57:46 +01:00
Marcio Ribeiro
7f13961884 soc: esp32: replace hard-coded addresses and sizes by DT macros
Replaces hard-coded memory addresses and sizes with macros that retrieve
such values from the device tree.

Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
2024-12-07 11:02:46 +01:00
Yong Cong Sin
e6dd68ec89 arch: riscv: introduce CONFIG_RISCV_GP_PURPOSE choice
Introduce `CONFIG_RISCV_GP_PURPOSE` choice to make sure that only
one of `CONFIG_RISCV_GP` or `CONFIG_RISCV_CURRENT_VIA_GP` can be
enabled, instead of relying of dependencies.

To do that, introduce a new
`CONFIG_RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING` that can be selected
by SoC when it implemented global pointer (GP) initialization for
relative addressing in its linker.

`CONFIG_RISCV_GP` will be the default choice when
`CONFIG_RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING=y`

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
2024-11-28 12:51:09 +01:00
Lucas Tamborrino
cdbd2b5558 soc: espressif: Add hardware initialization
Bring hardware initialization to zephyr code base.

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2024-11-26 00:12:45 +01:00
Marek Matej
98d0a2bb34 soc: espressif: esp32c6 split cached area
Split the cached area and assign both parts IROM and DROM meaning. This
is necessary to overcome the esptool section merging issues.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2024-11-20 15:58:07 -05:00
Sylvio Alves
c7a592b3e0 soc: esp32c6: add Wi-Fi support
Enables Wi-Fi support.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2024-11-18 13:17:54 -05:00
Raffael Rostagno
c4b7903828 pinctrl: esp32c6: Fix for input/output enable flags
Fix missing input/output enable flags on pinctrl macro, which
wouldn't allow for driver to see and apply flags configuration
made in the device tree.

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
2024-11-08 11:36:21 -06:00
Sylvio Alves
a1a6e8a1a3 soc: esp32c6: update linker files
Add new wifi sections into iram area.
Add new functions to iram area.
Remove unused entries.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2024-10-27 20:53:48 -05:00
Marcio Ribeiro
7e7672cb4b bugfix: esp32: allows QIO and QOUT flash modes
Allows QIO and QOUT flash mode to work on:
- esp32s2
- esp32s3
- esp32c2
- esp32c3
- esp32c6

Fixes #73677

Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
2024-10-16 12:26:52 +02:00
Sylvio Alves
e48639e460 soc: esp32c6: add LLEXT linker entry
Make sure LLEXT sections are properly placed to avoid
orphan declaration.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2024-10-10 10:06:53 +02:00
Marek Matej
a1c4552ea9 soc: esp32c6: Add runtime heap symbols
Update the linker scripts to provide necessary symbols.
Fix static allocation size check.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2024-09-21 11:29:53 +02:00
Marek Matej
a0d7016e27 soc: espressif: Simple boot validity
Update CONFIG_ESP_SIMPLE_BOOT to exclude if CONFIG_MCUBOOT=y
Fix usage of the config according to actual definition.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2024-09-19 18:02:20 -04:00
Sylvio Alves
aa3dd674a9 soc: esp32xx: update flash initialization
Rework how flash is initialized in esp32 SoC.
"esp_flash_app_init()" will make sure proper cache handling
will be set in place.i

Fixes #77551

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2024-09-13 11:36:58 -05:00
Marcio Ribeiro
baf62b7a98 soc: esp32: XIP removed from Espressif targets
The way ESP32 XIP works (with MMU and cache) does no fit the way Zephyr XIP
is implemented, causing issues related to included Zephyr linker files.
Flash code still resides in flash for execution, but MMU/Cache handles it
in such way that XIP might not (or should not) be used with current Zephyr
approach. To address this problem, XIP configuration option is being
removed from Espressif targets.

Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
2024-08-31 06:47:52 -04:00
Raffael Rostagno
3ee2a62a55 pm: esp32c6: Power management support
Power management support (light/deep sleep) for ESP32C6

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
2024-08-15 11:59:08 -04:00
Alberto Escolar Piedras
c346c77a2a soc/espressif/esp32c6: Do not set HAS_PM or HAS_POWEROFF
The source files required for this features are not present
in the tree for this SOC.
So if CONFIG_PM or CONFIG_POWEROFF are enabled, there would
be a cmake failure.

Let's just indicate these features are not supported in
kconfig.

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2024-07-16 12:53:09 -04:00
Sylvio Alves
0c5d5f796f soc: espressif: disable RNG entropy before app runs
SARADC was kept enabled to feed RNG entropy peripheral,
adding instability to Wi-Fi connection. So we disable it
before app runs as RNG driver already got initial entropy values.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2024-07-11 16:19:55 -04:00
Sylvio Alves
3163680427 soc: esp32c6: remove idle source file
risc-v idle call is being fetched from arch/ implementation.
This soc file is not used and can be removed.

Fixes #75540

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2024-07-08 12:12:21 -04:00
Sylvio Alves
f65770c1a1 soc: esp32xx: always use section prologue with alignment
ESP32 requires proper alignment between sections. There are some
scenarios, as reported in #74533, that the section can
get shifted, causing runtime failure.
Making sure SECTION_PROLOGUE is used with ALIGN_WITH_INPUT
will guarantee its consistency.

Fixes #74533

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2024-06-28 21:00:11 -04:00
Marek Matej
6a7c8d789f soc: espressif: Update MCUboot segment size
- Fix the build issues with the insufficient memory for
  the MCUboot.
- Fix the sysbuild with MCUboot tests on all ESP32xx SoCs.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2024-06-26 09:01:25 -04:00
Alberto Escolar Piedras
6e977ae2d5 lib c/cpp: Move .ctor .init_array handling from C++ to kernel
* Move ctors and init_array from the CPP library
  to the kernel library, as this is common for both C
  and C++ and it is the kernel who is running it.
* Rename the hidden kconfig option CPP_STATIC_INIT_GNU
  STATIC_INIT_GNU instead.
* If STATIC_INIT_GNU is not selected verify there is
  constructors left behind.
* Rename common-rom-cpp.ld to common-rom-init.ld
* Rename z_cpp_init_static to z_init_static,
  and have the kernel always call it.

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Signed-off-by: Keith Packard <keithp@keithp.com>
2024-06-25 19:14:37 -04:00
Raffael Rostagno
9265c82313 soc: esp32c6: Kconfig and .ld updates, DTS and comments fix
Kconfig, .ld and comments fixing
Fixed address of UART1, WDT and RTC timer disabled by default

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
2024-06-14 18:51:46 -04:00
Raffael Rostagno
6096a10b9a drivers: clock_control: Refactor for ESP32C6
Added support for C6 to allow CPU clock config

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
2024-06-14 18:51:46 -04:00
Raffael Rostagno
67e43f6a81 drivers: intc: Fix for ESP32C6 interrupt sources allocation
Fix to properly allocate IRQs for interrupt sources over 60.
It also screens out non-allocatable IRQs used by the CPU.

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
2024-06-14 18:51:46 -04:00
Marek Matej
b3523c9bfa soc: espressif: add esp32-c6 support
Add basic support for esp32c6 SoC.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2024-06-14 18:51:46 -04:00