Pretty print XML reports with tab identation on levels for better
readability and ease text diff there as well.
Signed-off-by: Dmitrii Golovanov <dmitrii.golovanov@intel.com>
The testcase.classname properties in `twister_report.xml` and
`twister_suite_report.xml` now contain the full testsuite name
(without its path prefix) instead of just two its dot-separated
leftmost components. This way `twister_report.xml` testsuite container
has no duplicate testcase elements with the same `classname` and `name`
properties executing with --no-detailed-test-id for a project with same
testcase names in its 'sibling' suites, for example`tests/kernel/sleep`.
Signed-off-by: Dmitrii Golovanov <dmitrii.golovanov@intel.com>
Extend `--no-detailed-test-id` command line option: in addition to its
current behavior to exclude from a test Suite name its configuration path
prefix, also don't prefix each Ztest Case name with its Scenario name.
For example: 'kernel.common.timing' Scenario name, the same Suite name,
and 'sleep.usleep' test Case (where 'sleep' is its Ztest suite name
and 'usleep' is Ztest test name.
This way both TestSuite and TestCase names follow the same principle
having no parent object name prefix.
There is no information loss in Twister reports with this naming:
TestSuite is a container object for its TestCases, whereas TestSuite
has its configuration path as a property.
Signed-off-by: Dmitrii Golovanov <dmitrii.golovanov@intel.com>
Currently, MT25 flashes were running in 3-byte mode.
This is not compatible with the chip we use in our project (MT25QU01GBBB),
as only 128 Mbit of its 1 Gbit can be addressed.
Signed-off-by: Martin Stumpf <finomnis@gmail.com>
The user data size of the RFCOMM tx pool is zero. There is not enough
space to put the tx_meta data. Use CONFIG_BT_CONN_TX_USER_DATA_SIZE to
set the data size for the RFCOMM tx pool.
Signed-off-by: Make Shi <make.shi@nxp.com>
These functions can be used to join pthreads in a non-standard way.
The function pthread_tryjoin will not block and simply test whether the
thread has exited already. The function pthread_timed_join will only block
until the specified time. The functions are wrappers for calling the
k_thread_join with timeout K_NO_WAIT and with a specific timeout as opposed
to calling it with K_FOREVER.
Signed-off-by: Cla Galliard <clamattia@gmail.com>
To facilitate changing this driver, decouple rtio from functions not
specific to RTIO. This also requires moving the sdk driver handle
creation outside of the configure call. An effect of this is we can
stop initializing an unused sdk driver handle for the dma path.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
These changes:
* Fix the check of the word size to be more useful
- check min frame size instead of max
- check for min word size requirement
- add a clarifying comment about what the word size represents in
hardware since the nomenclature from zephyr does not match the nxp
references
* Add a clarifying comment about half duplex being supported by hardware
* Add LPSPI_ namespace to defines
* Change chip select error message to be more clear about the problem
* Move the check of the clock device being ready to the lpspi init,
instead of checking it every time on configure. It probably also makes
more sense to not ready the lpspi device if the clock is not ready.
* Move the bare-metal configuration of bit fields AFTER the SDK Init
call.
* Return the proper error code if clock control call errors.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add device definitions in dt to test drivers that handle
multiple "compatible"s by a single driver.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Compilation will fail if both adin2111 and adin1100 are used
at the same time.
Changing to define different unique names for the symbols
to avoid conflicts.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
To avoid compilation on boards that do not have arduino_i2c defined,
we will clarify that it is dependent on it.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
Disabling the memory slab pointer validation improves the performance
of the memory allocation sub-test by about 9%.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
Makes the validation of both allocated memory slab pointer and the
memory slab pointer to free configurable.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
Resets uart tx fifo during driver initialization to have a well defined
initial condition mainly preventing unwanted characters being sent
Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
We have now fully migrated to CRYPTO_ALT which is a superset, so, remove
unused CRYPTO module and it's related files.
Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
Most users won't be interested in the per-channel rules but only in the
country code, so, add a verbose option to hiden per-channel rules which
are too verbose.
Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
In order to prepare for extending the options, convert to getopt long
for easier parsing of options.
Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
No need for an extra step to enable feature in the driver as it clearly
depends on the supplicant feature.
Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
The API docs state that the uart_poll_out is a blocking call,
but it does not specify how long a call to this function should
block the calling thread. This is described in the UART driver
documentation.
This patch clarifies the API docs and alignes it with the driver
documentation.
Signed-off-by: Hubert Miś <hubert.mis@nordicsemi.no>
Add a testcase for the stm32F412 or stm32F413
configuring the SDIO clock at 48MHz from the PLLI2S
Tested on the stm32f413h disco kit.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add a function to compute the clock48 from the clock tree
of a stm32f412/f413 mcu. The value depends on its clock source
Requires to identify the PLL source HSE or HSI.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add a clk48Mhz node to the stm32f412 serie.
This clock is sourced by PLL_Q (default) or PLLI2S_Q
That 48MHz clock is used by the USB /SDMMC/RNG peripherals.
The sdmmc/SDIO clock is sourced by this CK48 (default)
or by the SYSCLOCK.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add the configuration of the PLL Q divider of main PLL
and I2S_Q of the PLLI2S toset the PLL48MHz clock which feeds
the USB, SDMMC, RNG through the RCC_DCKCFGR2 register.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add power domains for EDMA0's channels 6, 7, 14, and 15.
For QM these are identified as IMX_SC_R_DMA_2_*, while
for QXP thy are identified as IMX_SC_R_DMA_0_*.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
This has no address space and doesn't belong between peripheral
nodes. Move it up the DTSI for better visibility. No functional
change.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
imx8qm and imx8qxp have a couple of differences regarding
the peripheral address spaces and how the DT nodes are
configured, which is why using a generic DTSI (nxp_imx8.dtsi)
for the both of them is not right.
One of the differences between the two, which affects Zephyr
is the fact that irqstr's address space is different. Up until
now this has been dealt with at the board level (i.e:
imx8qxp_mek_mimx8qx6_adsp.dts), which is not right as this is not
board-specific, but rather soc-specific. Additionally, this
causes the following warning during compilation:
"unit address and first address in 'reg' (0x51080000) don't
match for /interrupt-controller@510a0000"
To fix this, add two new DTSIs: nxp_imx8qm and nxp_imx8qxp.
Each board (i.e: imx8qm_mek and imx8qxp_mek) will have to include
the DTSI for their soc instead of the generic DTSI (i.e: nxp_imx8).
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Make sure that channels are inactive before releasing them.
This way, there won't be any leftover interrupts needed to be
handled when disabling IRQs.
This patch introduces a new state: CHAN_STATE_RELEASING. This is mostly
useful for the per-channel PD support in which the ISR needs to check
that the channel PD is enabled before attempting to access its register
space.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Commit 48b98a9284 ("drivers: dma: dma_nxp_edma: disable IRQs when
not needed") moved the IRQ enable operation to edma_start() and added
an IRQ disable operation in edma_stop(). This is wrong because it breaks
the DMA API contract w.r.t dma_start() being `isr-ok` on imx8qm/imx8qxp.
As such, move the IRQ enable and disable operations in
dma_request_channel() and dma_release_channel().
Note1: managing the interrupts like this is only really needed when
dealing with interrupt controllers that have a power domain associated
with it (which is the case for irqstr on imx8qm/imx8qxp).
Note2: Zephyr has no reference count for shared interrupts so disabling
a shared interrupt without checking if someone else is using it is
dangerous.
Based on the aforementioned notes, the irq_disable() operation is only
performed if irqstr is used as an interrupt controller (which is only
the case for imx8qm/imx8qxp). Otherwise, the operation isn't needed.
Fixes#80573.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
The channel state transitions are currently performed at the
beginning of each of the functions that triggers them
(e.g: edma_start(), edma_stop(), etc...). The main issue with
this approach is the fact if there's any failures after the state
transition then the channel will be in the target state without
performing the required steps for it.
For instance, during edma_config(), if any of the functions after
the state transition (the channel_change_state() call) fails
(e.g: get_transfer_type()) fails then the state of the channel
will be CONFIGURED even if not all the required steps were performed
(e.g: setting the MUX, configuring the transfer, etc...).
To fix this, split the state transition into two steps:
1) Check if the transition is possible.
2) Do the transition.
First step should be done before any configurations to make sure
that we should be performing them in the first place, while the
second step should be performed after all configurations, thus
guaranteeing that all the required steps for the target state were
performed before transitioning to it.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
