Add pinctrl and board enablement for LPUART2, which is broken out to
P4_2 and P4_3 on the FRDM board.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Automatically select CONFIG_GPIO when the GPIO-controlled CAN transceiver
driver is enabled. Update board configurations to benefit from this.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
In preparation for adding AMP support for i.MX RT6xx family we need
to rename existing cm33 support files to more specific names.
e.g mimxrt685_evk.dts -> mimxrt685_evk_mimxrt685s_cm33.dts
This will allow us to later add support for Cadence DSP found on i.MX
RT6xx series.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
imxrt6xx are dual core devices featuring an ARM Cortex-M33
core and an Cadence Xtensa HIFI4 Audio DSP.
Currently only m33 core is supported. In order to support
the Cadence DSP we need first to do some code-reorganization
for m33.
We start by moving all cm33 related code to its own directory
and introduce the cpuclusters property in soc.yml file.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Fixs USDHC by setting PWR and CD gpio's correctly.
Adds missing button from the GPS module.
Co-authored-by: Peter van der Perk <peter.vanderperk@nxp.com>
Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
Add pinctrl for SAI1 node. This means:
1) Adding definitions for the pads used by SAI1.
2) Creating a pin group and referencing it in
the SAI1 node via the `pinctrl-0` property.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Add pinctrl for SAI1 node. This means:
1) Adding definitions for the pads used by SAI1.
2) Creating a pin group and referencing it in the
SAI1 node via the `pinctrl-0` property.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Enable clock control for i.MX8ULP. This consists of:
1) Adding a PCC node in the DTS
2) Adding a header file containing the definitions
of the clocks used by the peripherals to be enabled.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Change, for audio DSP and M7 cores, SOC_<name> to match
the exact soc name.
Update the board files accordingly.
These configs are used in SOF and NXP_HAL, so change
sha for these modules.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
In future versions of Linkserver, specifying the core argument within
the device string will not be supported. Therefore, move the FRDM
MCXN947 board to specify the core directly instead of using the device
string.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
- fix schematic link pointing to different board
- fix link to the board_defconfig file
- remove the "Debug Firmware" link that was not referenced anywhere
- add a link to the board user manual
- minor additions to the debug with J-Link section
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Enable DMIC on RW612 BGA board. The DMIC is enabled for both onboard
MEMS microphones for this board, and the board is enabled with the DMIC
sample and test
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The SOC name `imx8ulp` has been just a placeholder until
support for the SOC's ADSP (since this is the only core
that's supported in Zephyr) could be added to the NXP HAL.
Now that the support has been added, to make use of it, the
SOC name `imx8ulp` has to be changed to `mimx8ud7`. As such,
this commit does the following:
1) Introduces SOC part number configuration - needed
by some HAL headers.
2) Replaces all occurrences of `imx8ulp` (as the SOC
name) with `mimx8ud7`.
3) Enables `CONFIG_HAS_MCUX`.
4) Aligns all `CONFIG_SOC_` configurations with the
new SOC name.
5) Updates SOF hash. This is needed to fix build issues
caused by this name change. This is not done in a separate
commit to preserve bisectability.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Add devicetree node for the accompanying, ssd1306-based display board
connected to connector P4.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Correct a few issues with the documentation that were causing rendering
issues, as well as the following changes:
- added blurb to debug section clarifying that the default debugger
firmware supports LinkServer
- updated serial terminal output with board name given when building
with HWMv2
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
By default, LinkServer's memory map for the MCXN947 does not define
memory regions for the SRAM or peripheral bus in secure mode. This
results in gdb failing to read from these memory regions unless
explicitly told ignore the debugger memory map via
"set mem inaccessible-by-default off".
To resolve this, define memory regions for SRAM and peripherals in
secure mode via the commandline arguments passed to LinkServer in
board.cmake.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Removes instances of setting CONFIG_BOARD that should have been
removed in the hwmv2 porting process
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Enable CTimer0 and MRT0 channel 0 by default on the board,
and add more of the device instances in the counter api test overlay.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Enable support for the mx25u51245g flash chip present on the
RD RW612 BGA. Support has been verified with the following samples:
- samples/drivers/flash_shell
- tests/drivers/flash/common
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
CAN requires 120 ohm termination at both ends of the bus, resulting in a
bus impedance of 60 ohm. Fix the board documentation to reflect this.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
This board fails to build for a multitude of samples & tests
which is blocking CI.
Let's provisionally disable it until the matter is properly
resolved.
The issue was introduced with the NXP HAL update to 2.15:
e4e463af81
See https://github.com/zephyrproject-rtos/zephyr/issues/69961
for more information.
Once this issue is fixed, this change should be reverted.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Enable support for dma controller on RD RW612 BGA board, and add overlay
to enable board in dma loop transfer test
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Remove all optional, initial CAN sample point properties and rely on the
CAN timing calculations to automatically pick the preferred sample point
location based on the initial bitrate.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Move the GPIO button dts nodes to the common dts file so it
be selected by either cpu core.
Also fix an error in the GPIO setting for one of the switches.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Update lpcxpresso55s69_cpu0 (and ns target) names in build commands in
the board documentation. Also, correct the documentation for dual core
images on this part, as it was out of date.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This board's twister yaml file claims to support the
arduino-serial tests, but it does not provide
the necessary DTS node, which is causing
failures in CI.
Let's remove the tag from the twister board definition.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
RD RW612 BGA board is built targeting secure mode execution. If
CONFIG_TRUSTED_EXECUTION_SECURE is not set, base address declarations in
CMSIS header files will be incorrect, causing a variety of issues. Fix
this.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
